This line is specified by the caption position register (address 00E016). This line is specified by the data slicer control register 3 (address 00EB16). The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the counter value matched the value specified by bits 4 to 0 of the caption position register (in case of the sub-data slice line, by bits 3 to 7 of the data slicer control register 3), this Hsep is sliced. The values of "0016" to "1F16" can be set in the caption position register. Bit 7 to bit 5 are used for testing. Set "1002." Figure 38 shows the signals in the vertical blanking interval. Figure 39 shows the structure of the caption position register.
2 Selection of field to be sliced data In the case of the main data slice line, the field to be sliced data is selected by bits 2 and 1 of the data slicer control register 1 (address 00EA16). In the case of the sub-data slice line, the field is selected by bits 2 and 1 of the data slicer control register 3. When bit 2 of the data slicer control register 1 is set to "1," it is possible to slice data of both fields (refer to Figures 32 to 34). 3 Specification of line to set slice voltage The reference voltage for slicing (slice voltage) is generated by integrating the amplitude of the clock run-in pulse in the particular line (refer to Table 4). 4 Field determination The field determination flag can be read out by bit 5 of the data slicer control register 1. This flag charge at the falling edge of Vsep.
Video signal
Vertical blanking interval
Composite video signal Vsep
Line 21
Hsep Count value to be set in the caption position register ("11 16" in this case)
Magnified drawing
Hsep Clock run-in Start bit + 16-bit data
Composite video signal
min. max. Time to be set in the start bit position register
Start bit
Fig. 38. Signals in Vertical Blanking Interval
43
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 4. Specifying of Field Whose Sets Reference Voltage Bit 0 of DSC3 0 1 Field specified by bit 1 of DSC1 Field specified by bit 1 of DSC3 Field 0: F2 0: F2 1: F1 1: F1 Line Line specified by bits 4 to 0 of CP (Main data slice line) Line specified by bits 7 to 3 of DSC3 (Sub-data slice line)
DSC1 : Data slice control register 1 DSC3 : Data slice control register 3 CP : Caption position register
(6) Reference Voltage Generating Circuit and Comparator
The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. 1 Reference voltage generating circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data
slice line specification circuit. Connect a capacitor between the VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. 2 Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value.
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 Caption Position Register (CP) [Address 00E0 16]
B
Name
Functions
After reset 0
RW RW
0 Specification main data to slice line (CP0 to CP4) 4 5, 6 Fix these bits to "0."
0
RW
7
Fix this bit to "0."
0
RW
Fig. 39. Caption Position Register
44
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(7) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line specification circuit. For start bit detection, it is possible to select one of the following two types by using bit 1 of clock run-in register 2 (address 00E716). 1After the lapse of the time corresponding to the set value of the start bit position register (address 00E116), the first rising of the composite video signal is detected as a start bit. The time is set in bits 0 to 6 of the start bit position register (address 00E116) (refer to Figure 40). Set a value fit for the following conditions. Figure 40 shows the structure of the start bit position register.
Time from the falling of the horizontal synchronizing signal to the last rising of the clock run-in
<
4 ! set value of the start bit position register ! reference clock period
<
Time from the faling of the horizontal synchronous signal to occurrence of the start bit
Start Bit Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Start bit position register (SP) [Address 00E116]
B 0 to 6
Name
Functions
After reset 0
RW RW
Start bit generating time Time from a falling of the horizontal (SP0 to SP6) synchronous signal to occurrence of a start bit = 4 ! set value ("0016" to "7F16") ! reference clock period DSC1 bit 7 control bit (SP7) 0 : Generation of 16 pulses 1 : Generation of 16 pulses and detection of clock run-in pulse (4 to 6 pulses)
7
0
RW
Fig. 40. Start Bit Position Register
45
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
2After a falling of the clock run-in pulse set in bits 2 to 0 of clock runin detect register 2 (address 00E916) is detected, a start bit is detected by sampling a comparator output. A sampling clock for sampling is obtained by dividing the reference clock generated in the timing signal generating circuit by 13.
Figure 42 shows the structure of clock run-in detect register 2. The contents of bits 2 to 0 of clock run-in detect register 2 and bit 1 of clock run-in register 2 are written at a falling of the horizontal synchronous signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronous signal.
Clock Run-in Register 2
b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 1 Clock run-in register 2 (CR2) [Address 00E716]
B
Name
Functions
After reset 0
RW RW
0, Fix these bits to "1." 2 to 4, 7 1 Start bit detecting method selection bit (CR21) Fix these bits to "0." 0: Method 1 1: Method 2
0
RW
5, 6
0
RW
Fig. 41. Clock Run-in Register 2
Clock Run-in Detect Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register 2 (CRD2) [Address 00E916]
B 0 to 2
Name Clock run-in pulses for sampling (CRD20 to CRD22) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions b0 0 : Not available 1 : 1st pulse 0 : 2nd pulse 1 : 3rd pulse 0 : 4th pulse 1 : 5th pulse 0 : 6th pulse 1 : 7th pulse
After reset 0
RW RW
3 to 7
Data clock generating time (CRD23 to CRD27)
Time from detection of a start bit to occurrence of a data clock = (13 + set value) ! reference clock period
0
RW
Fig. 42. Clock Run-in Detect Register 2
46
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(8) Clock run-in determination circuit
This circuit sets a window in the clock run-in portion in the composite video signal, and then determinates clock run-in by counting the number of pulses in this window. Set the time from a falling of the horizontal synchronizing signal to a start of the window by bits 0 to 5 of the window register (address 00E216; refer to Figure 43). The window ends according to the contents of the setting of the start bit position register (refer to Figure 40).
Window Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 Window register (WN) [Address 00E2 16]
B 0 to 5
Name Window start time (WN0 to WN5)
Functions Time from a falling of the horizontal synchronous signal to start of the window = 4 ! set value ("0016" to "3F16") ! reference clock period
After reset 0
RW RW
6, 7 Fix these bits to "0."
0
RW
Fig. 43. Window Register
47
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
For the main data slice line, the count value of pulses in the window is stored in clock run-in register 1 (address 00E616; refer to Figure 44). For the sub-data slice line, the count value of pulses in the window is stored in clock run-in register (address 020916; refer to Figure 45). When this count value is 4 to 6, it is determined as a clock run-in. Accordingly, set the count value so that the window may start after the first pulse of the clock run-in (refer to Figure 46). The contents to be set in the window register are written at a falling of the horizontal synchronous signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronous signal.
For the main data slice line, reference clock is counted in the period from a falling of the clock pulse set in bits 0 to 2 of clock run-in detect register 2 (address 00E916) to the next falling. The count value is stored in bits 3 to 7 of clock run-in detect register 1 (address 00E816) (When the count value exceeds "1F16," "1F16" is held). For the subdata slice line, the count value is stored in bits 3 to 7 of clock run-in detect register 3 (address 020816). Read out these bits after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). Figure 48 shows the structure of clock run-in detect registers 1 and 3.
Clock Run-in Register 1
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 Clock run-in register 1 (CR1) [Address 00E6 16]
B 0 to 3 4, 6
Name Clock run-in count value of main-data slice line (CR10 to CR13) Fix these bits to "1."
Functions
After reset 0
RW RW
0
RW
5, 7
Fix these bits to "0."
0
RW
Fig. 44. Clock Run-in Register 1
48
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Clock Run-in Register 3
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in register 3 (CR3) [Address 020916]
B 0 to 3 4
Name Clock run-in count value of sub-data slice line (CR30 to CR33) Data latch completion flag for caption data in subdata slice line (CR34)
Functions
After reset 0
RW RW
0: Data is not latched yet 1: Data is latched
Indeterminate R W
5
Data slice line selection bit for interrupt request (CR35) Interrupt mode selection bit (CR36)
0: Main data slice line 1: Sub- data slice line 0: Interrupt occurs at end of data slice line 1: Interrupt occurs at completion of caption data latch
Indeterminate R W
6
Indeterminate R W
7
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Indeterminate R --
Fig. 45. Clock Run-in Register 3
Horizontal synchronous signal Composite video signal Window
Clock run-in
Start bit data + 16-bit data
Time to be set in the window register Time to be set in the start bit position register
VWhen the count value in the window is 4 to 6, this is determined as a clock run-in.
Fig. 46. Window Setting
Clock Run-in Detect Register i
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register i (CRDi) (i=1, 3) [Addresses 00E816, 020816]
B 0 to 2 3 to 7
Name Test bits Read-only
Functions
After reset 0
RW RW
Clock run-in detection bits (CRDi3 to CRDi7)
Number of reference clock s to be counted one clock runin pulse period
0
R--
Fig. 47. Clock Run-in Detect Registers 1 and 3
49
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(9) Data clock generating circuit
This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. Set the time from detection of the start bit to occurrence of the data clock in bits 3 to 7 of clock run-in detect register 2 (address 00E916). The time to be set is represented by the following expression: Time = (13 + set value) ! reference clock period For a data clock, 16 pulses are generated. When just 16 pulses have Table 5. Setting Conditions for Caption Data Latch Completion Flag Bit 7 of SP 0 1 Conditions for Setting Bit 7 of DSC1 to "1" Data clock of 16 pulses has occured in main data slaice line Data clock of 16 pulses has occured in main data slaice line AND Clock run-in pulse are detected 4 to 6 times
been generated, bit 7 of the data slicer control register is set to "1" (refer to Figure 32 to 34). When method 1 is already selected as a start bit detecting method, this bit becomes a logical product (AND) value with a clock run-in determination result by setting bit 7 of the start bit position register to "1." When method 2 is already selected as a start bit detecting method and 16 pulses are generated of a data clock regardless of bit 7 of the start bit position register, this bit is set to "1." The contents of this bit are reset at a falling of the vertical synchronizing signal (Vsep).
Conditions for Setting Bit 4 of DSC3 to "1" Data clock of 16 pulses has occured in sub-data slaice line Data clock of 16 pulses has occured in sub-data slaice line AND Clock run-in pulse are detected 4 to 6 times
(10) 16-bit Shift Register
The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. For the main data slice line, the contents of the high-order 8 bits of the stored caption data and the contents of the low-order 8 bits of the same data can be obtained by reading out data register 2 (address 00E516) and data register 1 (address 00E416), respectively. For the sub-data slice line, the contents of the high-order 8 bits and the contents of the low-order 8 bits can be obtained by reading out the data register 4 (address 00ED16) and data register 3 (address 00EC16), respectively. These registers are reset to "0" at a falling of Vsep. Read out data registers 1 and 2 after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). Table 6. Occurence Sources of Interrupt Request CR3 b5 b6 0 0 0 1 1 0 0 1 1 1 1 0 Sub-data slice line CR2 b1 0 1 Main data slice line
(11) Interrupt Request Generating Circuit
The interrupt requests as shown in Table 6 are generated by combination of the following bits; bits 5 and 6 of the clock run-in register 3 (address 020916), bit 1 of the clock run-in register 2 (address 00E716). Read out the contents of data registers 1 to 4 and the contents of bits 3 to 7 of clock run-in detect registers 1 and 3 after the occurence of a data slicer interrupt request.
Occurence Souces of Interrupt Request Slice line At end of data slice line Data clock of 16 pulses has occured AND Clock run-in pulse are detected 4 to 6 times Data clock of 16 pulses has occured At end of data slice line Data clock of 16 pulses has occured AND Clock run-in pulse are detected 4 to 6 times Data clock of 16 pulses has occured Sources
50
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(12) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal Vsep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds "1F16," "1F16" is stored into the latch. The latch value can be obtained by reading out the sync pulse counter register (address 020F16). A count source is selected by bit 5 of the sync pulse counter register. The synchronous signal counter is used when bit 0 of PWM mode register 1 (address 02EA16). Figure 48 shows the structure of the sync pulse counter and Figure 49 shows the synchronous signal counter block diagram.
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (SYC) [Address 020F16]
B 0 to 4 5
Name Count value (SYC0 to SYC4) Count source (SYC5)
Functions
After reset 0
RW R--
0: HSYNC signal 1: Composite sync signal
0
RW
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Fig. 48. Sync Pulse Counter Register
f(XIN)/213
Composite sync signal HSYNC signal
Reset 5-bit counter Counter
b5 Selection gate : connected to black colored side when reset.
Latch (5 bits)
Sync pulse counter register
Data bus
Fig. 49. Synchronous Signal Counter Block Diagram
51
MITSUBISHI MICROCOMPUTERS
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament otic par N e Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 50 shows a block diagram of the multi-master I2C-BUS interface and Table 7 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits.
Table 7. Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
: System clock = f(XIN)/2 Note: We are not responsible for any third party's infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
b7
I2C address register (S0D)
b0
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
b7
I 2 C data shift register S0
b0 b7
MST TRX BB PIN
b0
AL AAS AD0 LRB
AL circuit
Internal data bus
I 2 C status register (S1)
BB circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE
b7
BSEL1 BSEL0 10BIT SAD ALS
b0
ESO BC2 BC1 BC0
I2 C clock control register (S2) Clock division
I2C clock control register (S1D) System clock ( ) Bit counter
Fig. 50. Block Diagram of Multi-master I2C-BUS Interface
52
MITSUBISHI MICROCOMPUTERS
. e. tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
PRE
L
A IMIN
RY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00F916) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are "1," the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616]
2
B 0 to 7
Name D0 to D7
Functions This is an 8-bit shift register to store receive data and write transmit data.
After reset
RW
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Fig. 51. I2C Address Register
53
MITSUBISHI MICROCOMPUTERS
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament otic par N e Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(2) I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave ___ address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. ____ s Bit 0: Read/Write Bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected. s Bits 1 to 7: Slave Address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716] B
0 1 to 7
Name
Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write
Functions
After reset R W
0 0
R-- RW
The address data transmitted from the master is compared with the contents of these bits.
Fig. 52. I2C Address Register
54
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(3) I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. s Bits 0 to 4: SCL Frequency Control Bits (CCR0-CCR4) These bits control the SCL frequency. Refer to Table 7. s Bit 5: SCL Mode Specification Bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is set. When the bit is set to "1," the high-speed clock mode is set. s Bit 6: ACK Bit (ACK BIT) This bit sets the SDA status when an ACK clockV is generated. When this bit is set to "0," the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). VACK clock: Clock for acknowledgement
s Bit 7: ACK Clock Bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0," the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I 2C clock generator is reset, so that data cannot be transmitted normally.
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2 : address 00FA16)
B
0 to 4
Name
Functions
High speed clock mode
After reset R W
0
SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) CCR4-CCR0 mode 00 to 02 03 04 05 06 1D 1E 1F ...
RW
Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3
500/CCR value
333 250 400 (See note) 166
1000/CCR value
17.2 16.6 16.1
34.5 33.3 32.3 0
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock
RW RW RW
6 7
0 0
Note: At 4000kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
Fig. 53. I2C Address Register
55
MITSUBISHI MICROCOMPUTERS
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) I2C Control Register
The I2C control register (address 00F916) controls the data communication format. s Bits 0 to 2: Bit Counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. s Bit 3: I2C Interface Use Enable Bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to "0," the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ESO = "0," the following is performed. PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I2C status register at address 00F816 ). Writing data to the I2C data shift register (address 00F616) is disabled.
* *
s Bit 4: Data Format Selection Bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "(5) I2C Status Register," bit 1) is received, transmission processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized. s Bit 5: Addressing Format Selection Bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. s Bits 6 and 7: Connection Control Bits between I2C-BUS Interface and Ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 55).
"0" "1" BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA "0" "1" BSEL1 SCL2/P12 "0" "1" BSEL0 SDA1/P13 "0" "1" BSEL1 SDA2/P14
Note: When using multi-master I2C-BUS interface, set bits 3 and 4 of the serial I/O mode register (address 021316) to "1." Moreover, set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface. Fig. 54. Connection Port Control by BSEL0 and BSEL1
56
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D : address 00F9 16)
B
0 to 2
Name
Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0: 1: 0: 1: 0: 1: 0: 1:
Functions
8 7 6 5 4 3 2 1
After reset R W
0
RW
3 4 5
I2 C-BUS interface use enable bit (ESO) Data format selection bit (ALS) Addressing format selection bit (10BIT SAD)
0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits between I2C-BUS interface and ports
Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output.
Fig. 55. I2C Control Register
57
MITSUBISHI MICROCOMPUTERS
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament otic par N e Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(5) I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. s Bit 0: Last Receive Bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). s Bit 1: General Call Detecting Flag (AD0) This bit is set to "1" when a general callV whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. VGeneral call: The master transmits the general call address "0016" to all slaves. s Bit 2: Slave Address Comparison Flag (AAS) This flag indicates a comparison result of address data. 1 In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions. The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00F716). A general call is received. 2 In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition. When the address data is compared with the I 2C address register (8 bits consists of slave address and RBW), the first bytes match. 3 The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00F616). s Bit 3: Arbitration LostV Detecting Flag (AL) In the master transmission mode, when a device other than the microcomputer sets the SDA to "L,", arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device.
* * *
generation is disabled. Figure 57 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in any one of the following conditions. Executing a write instruction to the I2C data shift register (address 00F616). When the ESO bit is "0" At reset The conditions in which the PIN bit is set to "0" are shown below: Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) Immediately after completion of 1-byte data reception In the slave reception mode, with ALS = "0" and immediately after completion of slave address or general call address reception In the slave reception mode, with ALS = "1" and immediately after completion of address data reception s Bit 5: Bus Busy Flag (BB) This bit indicates the status of use of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. When this bit is set to "1," this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ESO bit of the I2C control register (address 00F916) is "0" and at reset, the BB flag is kept in the "0" state.
* * * * * * *
VArbitration lost: The status in which communication as a master is disabled. s Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from "1" to "0." At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to "0" in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock
58
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s Bit 6: Communication Mode Specification Bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00F916) is "0" in the slave reception mode is selected, the TRX bit is set to "1" __ (transmit) if the least significant bit (R/W bit) of the address data_ trans_ mitted by the master is "1." When the ALS bit is "0" and the R/W bit is "0," the TRX bit is cleared to "0" (receive). The TRX bit is cleared to "0" in one of the following conditions. When arbitration lost is detected. When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication prevention function (Note). With MST = "0" and when a START condition is detected. With MST = "0" and when ACK non-return is detected. At reset
* * * * * *
s Bit 7: Communication Mode Specification Bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in one of the following conditions. Immediately after completion of 1-byte data transmission when arbitration lost is detected When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). At reset
* * * *
Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: * a START condition is set by another master device.
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " 0 : No general call detected 1 : General call detected 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
After reset R W
Indeterminate 0 0 0 0 0 0
R-- R-- R-- R-- R-- RW RW
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
Fig. 56. I2C Status Register
59
MITSUBISHI MICROCOMPUTERS
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
SCL PIN
IICIRQ
Fig. 57. Interrupt Request Signal Generation Timing
(6) START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) to set the MST, TRX and BB bits to "1." A START condition will then be generated. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 58 for the START condition generation timing diagram, and Table 8 for the START condition/STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag
Fig. 58. START Condition Generation Timing Diagram
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence: 1Set "2016" to the I2C status register (S1). 2Write a transmit data to the I2C data shift register. 3Set "F016" to the I2C status register (S1) again. I2C status register ; S1 = 2016 I2C data shift register ; S0 = transmit data after restart I2C status register ; S1 = F016
60
MITSUBISHI MICROCOMPUTERS
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(8) STOP Condition Generation Method
When the ES0 bit of the I2C control register (address 00F916) is "1," execute a write instruction to the I2C status register (address 00F816) for setting the MST bit and the TRX bit to "1" and the BB bit to "0". A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 51 for the STOP condition generation timing diagram, and Table 8 for the START condition/STOP condition generation timing table.
(9) START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in Figure 52 and Table 9. Only when the 3 conditions of Table 9 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" is generated to the CPU.
I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag
SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time Hold time
Fig. 59. STOP Condition Generation Timing Diagram
Fig. 60. START Condition/STOP Condition Detect Timing Diagram
Table 8. START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode High-speed Clock Mode Setup time 5.0 s (20 cycles) 2.5 s (10 cycles) Hold time 5.0 s (20 cycles) 2.5 s (10 cycles) Set/reset time 3.0 s (12 cycles) 1.5 s (6 cycles) for BB flag Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
Table 9. START Condition/STOP Condition Detect Conditions High-speed Clock Mode Standard Clock Mode 1.0 s (4 cycles) < SCL 6.5 s (26 cycles) < SCL release time release time 3.25 s (13 cycles) < Setup time 0.5 s (2 cycles) < Setup time 3.25 s (13 cycles) < Hold time 0.5 s (2 cycles) < Hold time Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
61
MITSUBISHI MICROCOMPUTERS
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 61, (1) and (2). 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00F916) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address regis__ ter (address 00F716) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit __ addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to "1." After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00F716) to "1" by __ software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 61, (3) and (4).
Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 00FA16). Set "1016" in the I2C status register (address 00F816) and hold the SCL at the HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). When a START condition is received, an address comparison is made. *When all transmitted addresses are "0" (general call) : AD0 of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. *When the transmitted addresses match the address set in : AAS of the I2C status register (address 00F816) is set to "1" and an interrupt request signal occurs. *In the cases other than the above : AD0 and AAS of the I2C status register (address 00F816) are set to "0" and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00F616). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends.
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00F716) and "0" in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 00FA16). Set "1016" in the I2C status register (address 00F816) and hold the SCL at the HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00F916). Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00F616) and set "0" in the least significant bit. Set "F016" in the I2C status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs.
62
MITSUBISHI MICROCOMPUTERS
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
S
Slave address R/W
A
Data
A
Data
A/A
P
7 bits "0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
A
P
7 bits "1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte
S
A
A
Data
A
Data
A/A
P
7 bits "0" 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits
S
A
A
Sr
Data
A
Data 1 to 8 bits
A
P
7 bits "0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master
Fig. 61. Address Data Communication Format
63
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD FUNCTIONS
Table 10 outlines the OSD functions of the M37274EFSP. The M37274EFSP incorporates an OSD circuit of 40 characters ! 16 lines. OSD is controlled by the OSD control register. There are 3 display modes and they are selected by a block unit. The display modes are selected by block control register i (i = 1 to 16). The features of each mode are described below.
Note : Note that MASK version has 36 characters ! 12 lines when programming.
Table 10. Features of Each Display Mode Parameter Number of display characters Character display area Kinds of characters Kinds of character sizes Pre-divide ratio (Note) Dot size Attribute Character font coloring Raster coloring Character background coloring Border coloring Extra font coloring OSD output Function R, G, B, OUT1, OUT2 Auto solid space function Window function Dual layer OSD function (layer 1) Possible R, G, B, OUT1, OUT2 Dual layer OSD function (layer 2) CC Mode (Closed caption mode) Display Mode OSD Mode (On-screen display mode) 40 characters ! 16 lines 16 ! 26 dots 16 ! 20 dots 16 ! 26 dots (character dot structure : 20 ! 16 dots) 256 kinds (In EXOSD mode, they can be combined with 16 kinds of extra fonts) 2 kinds 14 kinds 6 kinds ! 1, ! 2 ! 1, ! 2, ! 3 ! 1, ! 2, ! 3 1TC ! 1/2H Smooth italic, under line, flash 1 screen : 7 kinds, Max. 7 kinds (a character unit) 1TC ! 1/2H, 1TC ! 1H, 1.5TC ! 1/2H, 1.5TC ! 1H, 2TC ! 2H, 3TC ! 3H Border 1 screen : 7 kinds, Max. 7 kinds (a character unit) 1TC ! 1/2H, 1TC ! 1H Border, extra font (16 kinds) 1 screen : 5 kinds, Max. 5 kinds (a character unit) EXOSD Mode (Extra on-screen display mode)
Possible (a screen unit, 1 screen : 7 Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : kinds, max. 7 kinds) 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Possible (a character unit, 1 screen Possible (a character unit, 1 screen Possible (a character unit, 1 screen : : 7 kinds, max. 7 kinds) : 7 kinds, max. 7 kinds) 7 kinds, max. 5 kinds) Possible (a screen unit, 1 screen : Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) 7 kinds, max. 7 kinds) Possible (a screen unit, 1 screen : 7 kinds, max. 7 kinds) R, G, B, OUT1, OUT2
Possible Possible Display expansion (multiline display) Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as "pre-divide ratio" hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to (3) Dote size).
64
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 62 shows the configuration of OSD character. Figure 63 shows the block diagram of the OSD circuit. Figure 64 shows the structure of the OSD control register. Figure 65 shows the structure of the block control register i.
CC mode OSD mode
16 dots 16 dots Blank area V
20 dots
26 dots 20 dots
Underline area V Blank area V
V : Displayed only in CCD mode.
EXOSD mode
16 dots 16 dots 16 dots
20 dots
26 dots
logical sum (OR)
Character font
Extra font
Fig. 62. Configuration of OSD Character Display Area
26 dots
65
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Main clock XIN XOUT
Clock for OSD OSC1 OSC2 HSYNC VSYNC
Oscillation circuit
Display oscillation circuit
Data slicer clock
Control registers for OSD OSD Control circuit OSD control register Horizontal position register Block control registers Clock source control register I/O polarity control register Raster color register Extra font color register Border color register Window H/L registers Vertical position registers RAM for OSD
20 bytes !40 characters !16 lines
(address 00CE16) (address 00CF16) (addresses 00D016 to 00DF16) (address 021616) (address 021716) (address 021816) (address 021916) (address 021B16) (addresses 021C16 to 021F16) (addresses 022016 to 023F16)
ROM for OSD
(16 dots! 20 dots! 256 characters) + 16 dots! 26 dots! 16 characters)
Shift register 1 16-bit Output circuit Shift register 2 16-bit
R
G
B
OUT1
OUT2
Data bus
Fig. 63. Block Diagram of OSD Circuit
66
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic ice: aram Not e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (OC) [Address 00CE16] B 0 1 2 3 Name OSD control bit (OC0) (See note 1) Scan mode selection bit (OC1) Border type selection bit (OC2) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Normal scnan mode 1 : Bi-scan mode 0 : All bordered 1 : Shadow bordered (See note 2) After reset R W 0 0 0 0 RW RW RW RW
Flash mode selection 0 : Color signal of character background bit (OC3) part does not flash 1 : Color signal of character background part flashes 0 : OFF 1 : ON 0 : OFF 1 : ON
b7 b6
4 Automatic solid space control bit (OC4) 5 Window control bit (OC5) 6, 7 Layer mixing control bits (OC6, OC7) (See note 3)
0 0
RW RW
0 0: Logic sum (OR) of layer 1's color and layer 2's color 0 1: Layer 1's color has priority 1 0: Layer 2's color has priority 1 1: Do not set.
0
RW
Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next V SYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : Set "00" during displaying extra fonts.
Fig. 64. OSD Control Register
Block Control register i
b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16](See note 1) B Name
b1 b0
Functions 0 0 1 1 0: Display OFF 1: OSD mode 0: CC mode 1: EXOSD mode
After reset
RW
0, 1 Display mode selection bits (BCi0, BCi1)
Indeterminate R W
2
Border control bit (BCi2)
0: Border OFF 1: Border ON
b6 b5 b4 b3 CS6 Pre-divide ratio Dot size Display layer
Indeterminate R W Indeterminate R W
3, 4 Dot size selection bits (BCi3, BCi4)
0
0
0
1
5, 6 Pre-divide ratio * layer selection bit (BCi5, BCi6)
1
0
1
1
1
1
0 0 1 1 0 0 1 1 0 0 1 1 -- -- 0 0 1 1
0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
--
!1
--
!2
--
!3 !1
0
1
!2
1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H 1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H Layer1 3Tc ! 3H 1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H 1Tc ! 1/2H 1Tc ! 1H Layer2 1Tc ! 1/2H 1Tc ! 1H 1.5Tc ! 1/2H 1.5Tc ! 1H
Indeterminate R W
7
OUT2 output control bit (BCi7) (See note 2)
BC17: Window top boundary BC27: Window bottom boundary
Indeterminate R W
Notes 1: Note that MASK version the block control registers at addresses 00D0 when programming. 2: Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0". Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1". 3: CS6 : Bit 6 of the clock control register (address 0216 16) 4: Tc : Pre-devided clock period for OSD 5: H : Hsync
16
to 00DB16
Fig. 65. Block Control Registers
67
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(1) Dual Layer OSD
M37274MA-XXXSP has 2 layers; layer 1 and layer 2. These layers display the OSD for controlling TV and the closed caption display at the same time and overlayed on each other. Each block can be assigned to either layer by bits 6 and 5 of the block control register (refer to Figure 65). For example, only when both bits 5 and 6 are "1," the block is assigned to layer 2. Other bit combinations assign the block to layer 1. When a block of layer 1 is overlapped with that of layer 2, a screen is combined (refer to Figure 67) by bits 7 and 6 of the OSD control register (refer to Figure 64). Note: When using the dual layer OSD, note Table 11.
Layer 2 Block 9 Block 10 Block 11 Block 12 Block Block 1 Block 2
Block 7 Block 8 Block Layer 1
...
Fig. 66. Image of Dual Layer OSD
Table 11. Conditions of Dual Layer Block Parameter Display mode OSD Clock source Pre-divide ratio Dot size Horizontal display start position Block in Layer 1 CC mode Data slicer clock or OSC1 or main clock ! 1 or ! 2 (all blocks) 1TC ! 1/2H Arbitrary Block in Layer 2 OSD mode Same as layer 1 Same as layer 1 (Note) Pre-divide ratio = 1 1TC ! 1/2H 1TC ! 1H Pre-divide ratio = 2 1TC ! 1/2H, 1.5TC ! 1/2H 1TC ! 1H, 1.5TC ! 1H
Same position as layer 1
Note: For the pre-divide ratio of the layer 2, select the same as the layer 1's ratio by bit 6 of the clock control register.
Display example of layer 1 = "HELLO," layer 2 = "CH5"
CH5 HELLO
CH5 HELLO
CH5 HELLO
Logical sum (OR) of layer 1's color and layer 2's color Bit 7 = "0," bit 6 = "0"
Layer 1's color has priority Bit 7 = "0", bit 6 = "1"
Layer 2's color has priority Bit 7 = "1," bit 6 = "0"
Fig. 67. Display Example of Dual Layer OSD
68
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(2) Display Position
The display positions of characters are specified by a block. There are 16 blocks, blocks 1 to 16. Up to 40 characters can be displayed in each block (refer to (6) Memory for OSD). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 TOSC (TOSC = OSD oscillation cycle). The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 TH ( TH = HSYNC cycle).
Blocks are displayed in conformance with the following rules: 1 When the display position is overlapped with another block (Figure 68, (b)), a lower block number (1 to 16) is displayed on the front. 2 When another block display position appears while one block is displayed (Figure 68 (c)), the block with a larger set value as the vertical display start position is displayed. However, do not display block with the dot size of 2TC ! 2H or 3TC ! 3H during display period ( V ) of another block. V In the case of OSD mode block: 20 dots in vertical from the vertical display start position. V In the case of CC or EXOSD mode block: 26 dots in vertical from the vertical display start position.
(HR) VP11, VP21 Block 1 VP12, VP22 Block 2 VP13, VP23 Block 3
(a) Example when each block is separated
(HR) VP11, VP12 = VP21, VP22 Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1
(HR) VP11, VP21 VP12, VP22 Block 1 Block 2 (c) Example when block 2 overlaps in process of block 1
Note: VP1i or VP2i (i : 1 to 16) indicates the vertical display start position of display block i.
Fig. 68. Display Position
69
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the I/O polarity control register (address 021716).
8 machine cycles or more VSYNC signal input 0.25 to 0.50 [s] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal (Note 2) HSYNC signal input 8 machine cycles or more 1 2 3 4 5
Not count When bits 0 and 1 of the I/O polarity control register (address 021716) are set to "1" (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of V SYNC control signal in the microcomputer. 2 : Do not generate falling edge of H SYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more.
Fig. 69. Supplement Explanation for Display Position
70
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH: HSYNC cycle)) as values "0016" to "FF16" in vertical position register 1i (i = 1 to 12) (addresses 022016 to 022B16)
and values "0016" to "0316" in vertical position register 2i (i = 1 to 12) (addresses 023016 to 023B16). The structure of the vertical position registers is shown in Figure 70 and 71.
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16] B Name Functions After reset RW
0 Control bits of vertical Vertical display start positions Indeterminate R W to display start positions (low-order 8 bits) 7 (VP1i0 to VP1i7) TH ! (See note 1) (setting value of low-order 2 bits of VP2i ! 162 + setting value of low-order 4 bits of VP1i ! 161 + setting value of low-order 4 bits of VP1i ! 160) Notes 1: Set values except "00 16" "0116" to VP1i when VP2i is "00 16." 2: TH is cycle of HSYNC.
Fig. 70. Vertical Position Register 1
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16] B Name Functions After reset RW
0, 1 Control bits of vertical Vertical display start positions Indeterminate R W display start positions (high-order 2 bits) TH ! (VP1i0, VP1i1) (See note 1) (setting value of low-order 2 bits of VP2i ! 162 + setting value of low-order 4 bits of VP1i ! 161 + setting value of low-order 4 bits of VP1i ! 160) 2 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are indeterminate. 7 Indeterminate R --
Notes 1: Set values except "00 16" "0116" to VP1i when VP2i is "00 16." 2: TH is cycle of HSYNC.
Fig. 71. Vertical Position Register 2
71
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle for display) as values "0016" to "FF16" in bits 0 to 7 of the horizontal position register (address 00CF16). The structure of the horizontal position register is shown in Figure 72.
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00CF16] B Name Functions Horizontal display start positions
4TOSC ! (setting value of high-order 4 bits ! 161 + setting value of low-order 4 bits ! 160 )
After reset R W 0 RW
0 Control bits of horizontal to display start positions 7 (HP0 to HP7)
Notes 1. The setting value synchronizes with the V SYNC. 2. TOSC = OSD oscillation period.
Fig. 72. Horizontal Position Register
72
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different predivide ratios, their horizontal display start position will not match. Ordinaly, this gap is 1TC regardless of character sizes, however, the gap is 1.5TC only when the character size is 1.5TC.
2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their horizontal display start position will not match.
HSYNC 1TC 4TOSC ! N
Block 1 (Pre-divide ratio = 1, clock source = data slicer clock) Block 2 (Pre-divide ratio = 2, clock source = data slicer clock)
1TC 1TC
Block 3 (Pre-divide ratio = 3, clock source = data slicer clock)
Note 1
1.5TC
Block 4 (Pre-divide ratio = 2, character size = 1.5Tc, clock source = data slicer clock)
Note 2
4TOSC' ! N
1TC
Block 5 (Pre-divide ratio = 3, clock source = OSC1) N : Value of horizontal position register (decimal notation) 1Tc : OSD clock cycle divided in the pre-divide circuit Tosc : OSD oscillation cycle
Fig. 73. Notes on Horizontal Display Start Position
73
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(3) Dot Size
The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1, main clock) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1TC. The dot size of the layer 1 is specified by bits 6 to 3 of the block control register. The dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. Refer to Figure 65 (the structure of the block control regis-
ter), refer to Figure 76 (the structure of the clock source control register). The block diagram of dot size control circuit is shown in Figure 75. Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode. 2 : The pre-divide ratio of the OSD mode block on the layer 2 must be same as that of the CC mode block on the layer 1 by bit 6 of the clock source control register. 3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. Refer to "(13) Scan Mode" about the scan mode.
Main clock OSC1 Data slicer clock (Note)
Synchronous
circuit
Clock cycle = 1TC
Cycle ! 2 Cycle ! 3
Horizontal dot size control circuit
Pre-divide circuit HSYNC Vertical dot size control circuit
OSD control circuit Note: To use data slicer clock, set bit 0 of data slicer control register to "0."
Fig. 74. Block Diagram of Dot Size Control Circuit
1 dot
1TC 1/2H 1H
1TC
2TC
3TC Scanning line of F1(F2) Scanning line of F2(F1) 3H
2H
In normal scan mode
Fig. 75. Definition of Dot Sizes
74
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(4) Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 4 types. Main clock (8 MHz) Data slicer clock output from the data slicer (approximately 26 MHz) Clock from the LC oscillator supplied from the pins OSC1 and OSC2 Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the port P3 direction register, bits 5 and 4 of the clock source control register (addresses 021616). A variety of character sizes can be obtained by combining dot sizes with OSD clocks. When not using the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P6.
Table 12. Setting for P63/OSC1/XCIN, P64/OSC2/XCOUT Sub-clock Input OSD Clock Function I/O Pin Port I/O Pin Register b7 of port P3 direction register Clock source control register b5 b4 1 0 1 1 0 0 0 1 0 0 1
* * * *
Data slicer circuit 32 kHZ
"00"
(Note) Data slicer clock
"0" Except "10" "1" "0"
CS0
"10"
CC mode block CS2, CS1
Except "10"
OSC1 clock LC
Ceramic * quartz-crystal "10"
"1" "0"
CS1 CS2 = "0"
OSD mode block CS2, CS1
Except "10"
CS5, CS4
"11"
"1"
CS3
"10"
EXOSD mode block CS2, CS1
Oscillating mode for OSD Clock oscillation circuit
Main clock
Note : To use data slicer clock, set bit 0 of data slicer control register to "1."
Fig. 76. Block Diagram of OSD Selection Circuit
75
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Clock Source Control Register
b7 b6 b5 b4 b3 b2 b1 b0 Clock source control register (CS) [Address 021616]
B 0
Name CC mode clock selection bit (CS0)
Functions 0: Data slicer clock 1: OSC1 clock
b2 b1
After reset R W 0 0 RW RW
1, 2 OSD mode clock selection bits (CS1, CS2)
0 0 1 1
0: Data slicer clock 1: OSC1 clock 0: Main clock (See note 1) 1: Do not set 0 0 RW RW
3
EXOSD mode clock selection bit (CS3)
0: Data slicer clock 1: OSC1 clock
b5 b4
4, 5 OSD oscillating mode selection bits (CS4, CS5)
0 0: 32 kHz oscillating mode 0 1: Input ports P63, P64 (See note 2) 1 0: LC oscillating mode 1 1: Ceramic * quartz-crystal oscillating mode 0: ! 1 1: ! 2 0
0
6 7
Pre-divide ratio of layer 2 selection bit (CS6) Test bit (See note 3)
RW
RW
Notes 1: When setting "102," main clock is set as a clock in the CC mode and EXOSD mode regardless of bits 0, 3. 2: When selecting input ports P63 and P64, set bit 7 at address 00C716 to "0." 3: Be sure to set bit 7 to "0" for program of the mask and the EPROM versions. For the emulator MCU version (M37274ERSS), be sure to set bit 7 to "1" when using the data slicer clock for software debugging.
Fig. 77. Clock Control Register
76
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(5) Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 79) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC control signal (refer to Figure 69) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is regarded as odd field The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control register at address 021716). A dot line is specified by bit 6 of the I/O polarity control register (refer to Figure 79). However, the field determination flag read out from the CPU is fixed to "0" at even field or "1" at odd field, regardless of bit 6.
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 021716]
B 0 1 2 3 4 5 6
Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2) Fix this bit to "0". OUT1 output polarity switch bit (PC4) OUT2 output polarity switch bit (PC5) Display dot line selection bit (PC6) (See note)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output
After reset R W 0 0 0 0 RW RW RW R-- RW RW RW
0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0:" " 1:" " " at even field " at odd field " at even field " at odd field
0 0 0
7
Field determination flag (PC7)
0 : Even field 1 : Odd field
1
R--
Note: Refer to Figure 79.
Fig. 78. I/O Polarity Control Register
77
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Both HSYNC signal and VSYNC signal are negative-polarity input Field Display dot line determination selection bit flag(Note)
HSYNC
Field
Display dot line
VSYNC and VSYNC control signal in microcomputer Upper : VSYNC signal Lower : VSYNC control signal in microcomputer
(n - 1) field (Odd-numbered) T1
0.25 to 0.50[s] at f(XIN) = 8 MHz
Odd
0 (n) field (Even-numbered) T2 Even 0 (T2 > T1) 1
Dot line 1 Dot line 0
0 (n + 1) field (Odd-numbered) T3 Odd 1 (T3 < T2) 1
16)
Dot line 0
Dot line 1 to "0."
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CC mode * EXOSD mode 2345 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OSD mode 12 345
6 7 8 9 10 11 12 13 14 15 16
When the display dot line selection bit is "0," the " " font is displayed at even field, the " " font is displayed at odd field. Bit 7 of the I/O polarity control register can be read as the field determination flag : "1" is read at odd field, "0" is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in the microcomputer.
Fig. 79. Relation between Field Determination Flag and Display Font
78
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic ice: aram Not e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(6) Memory for OSD
There are 2 types of memory for OSD : ROM for OSD (addresses 1080016 to 155FF16, 1800016 to 1E41F16) used to store character dot data (masked) and RAM for OSD (addresses 080016 to 0DF316) used to specify the characters and colors to be displayed. The following describes each type of memory. 1 ROM for OSD (addresses 1080016 to 155FF16, 1800016 to 1E43F16) The ROM for OSD contains dot pattern data for characters to be displayed. To actually display the character code and the extra code
stored in this ROM, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the ROM for OSD) into the RAM for OSD. The OSD ROM of the character font has a capacity of 11072 bytes. Since 40 bytes are required for 1 character data, the ROM can stores up to 256 kinds of characters. The OSD ROM of the extra font has a capacity of 832 bytes. Since 52 bytes are required for 1 character data, the ROM can stores up to 16 kinds of characters. Data of the character font and extra font is specified shown in Figure 80.
OSD ROM address of character font data
OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit
Line number/character code/font bit
1
0
Line number
0
Character code
= "0216" to "1516" Line number Character code = "0016" to "FFF16" Font bit = 0 : left font 1 : right font
OSD ROM address of extra font data
OSD ROM address bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit
Line number/extra code /font bit Line number Extra code Font bit Line number
0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516
1
1
Line number
0
0
0
0
0
Extra code
= "0016" to "1916" = "0016" to "0F16" = 0 : left font 1 : right font Left font Right font Data in Line OSD number ROM
000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916
b7
b7
b0 b7
b0
Left font
b0 b7
Right font
b0
Data in OSD ROM
FFFE16 FFFF16 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 000316 FFFF16 FFFE16 000016 000016
Character font
Extra font
Fig. 80. OSD Character Data Storing Form
79
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
2 RAM for OSD (addresses 080016 to 0FF716) The RAM for OSD is allocated at addresses 080016 to 0FF716, and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. Table 13 shows the contents of the RAM for OSD. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write color code 1 at 084016, and write color code 2 at 082816. The structure of the RAM for OSD is shown in Figure 82.
Note: For the OSD mode block with dot size of 1.5TC ! 1/2H and 1.5TC ! 1H, the 3nth (n = 1 to 13) character is skipped as compared with ordinary blockV. Accordingly, maximum 27 characters (the right 1/3 part of the 27th's character area is not displayed) are only displayed in 1 block. The RAM data for the 3nth character does not effect the display. Any character data can be stored here (refer to Figure 81). Mask version has maximum 24 characters in 1 block when programming. V Blocks with dot size of 1TC ! 1/2H and 1TC ! 1H, or blocks on the layer 1
Table 13. Contents of OSD RAM Block Display Position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character Code Specification 080016 080116 : 081716 081816 : 082616 082716 088016 088116 : 089716 0E9816 : 08A616 08A716 090016 090116 : 091716 091816 : 092616 092716 098016 098116 : 099716 099816 : 09A616 09A716 0A0016 0A0116 : 0A1716 0A1816 : 0A2616 0A2716 Color Code 1 Specification 084016 084116 : 085716 085816 : 086616 086716 08C016 08C116 : 08D716 08D816 : 08E616 08E716 094016 094116 : 095716 095816 : 096616 096716 09C016 09C116 : 09D716 08D816 : 09E616 09E716 0A4016 0A4116 : 0A5716 0A5816 : 0A6616 0A6716 Color Code 2 Specification 082816 082916 : 083F16 086816 : 087616 087716 08A816 08A916 : 08BF16 08E816 : 08F616 08F716 092816 092916 : 093F16 096816 : 097616 097716 09A816 09A916 : 09BF16 09E816 : 09F616 09F716 0A2816 0A2916 : 0A3F16 0A6816 : 0A7616 0A7716
Block 1
Block 2
Block 3
Block 4
Block 5
80
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 13. Contents of OSD RAM (continued) Block Display Position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character Code Specification 0A8016 0A8116 : 0A9716 0A9816 : 0AA616 0AA716 0B0016 0B0116 : 0B1716 0B1816 : 0B2616 0B2716 0B8016 0B8116 : 0B9716 0B9816 : 0BA616 0BA716 0C0016 0C0116 : 0C1716 0C1816 : 0C2616 0C2716 0C8016 0C8116 : 0C9716 0C9816 : 0CA616 0CA716 0D0016 0D0116 : 0D1716 0D1816 : 0D2616 0D2716 0D8016 0D8116 : 0D9716 0D9816 : 0DA616 0DA716 Color Code 1 Specification 0AC016 0AC116 : 0AD716 0AD816 : 0AE616 0AE716 0B4016 0B4116 : 0B5716 0B5816 : 0B6616 0B6716 0BC016 0BC116 : 0BD716 0BD816 : 0BE616 0BE716 0C4016 0C4116 : 0C5716 0C5816 : 0C6616 0C6716 0CC016 0CC116 : 0CD716 0CD816 : 0CE616 0CE716 0D4016 0D4116 : 0D5716 0D5816 : 0D6616 0D6716 0DC016 0DC116 : 0DD716 0DD816 : 0DE616 0DE716 Color Code 2 Specification 0AA816 0AA916 : 0ABF16 0AE816 : 0AF616 0AF716 0B2816 0B2916 : 0B3F16 0B6816 : 0B7616 0B7716 0BA816 0BA916 : 0BBF16 0BE816 : 0BF616 0BF716 0C2816 0C2916 : 0C3F16 0C6816 : 0C7616 0C7716 0CA816 0CA916 : 0CBF16 0CE816 : 0CF616 0CF716 0D2816 0D2916 : 0D3F16 0D6816 : 0D7616 0D7716 0DA816 0DA916 : 0DBF16 0DE816 : 0DF616 0DF716
Block 6
Block 7
Block 8
Block 9
Block 10
Block 11
Block 12
81
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Table 13. Contents of OSD RAM (continued) Block Display Position (from left) 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character 1st character 2nd character : 24th character 25th character : 39th character 40th character Character Code Specification 0E0016 0E0116 : 0E1716 0E1816 : 0E2616 0E2716 0E8016 0E8116 : 0E9716 0E9816 : 0FA616 0FA716 0F0016 0F0116 : 0F1716 0F1816 : 0F2616 0F2716 0F8016 0F8116 : 0F9716 0F9816 : 0FA616 0FA716 Color Code 1 Specification 0E4016 0E4116 : 0E5716 0E5816 : 0E6616 0E6716 0EC016 0EC116 : 0ED716 0ED816 : 0EE616 0EE716 0F4016 0F4116 : 0F5716 0F5816 : 0F6616 0F6716 0FC016 0FC116 : 0FD716 0FD816 : 0FE616 0FE716 Color Code 2 Specification 0E2816 0E2916 : 0E3F16 0E6816 : 0E7616 0E7716 0EA816 0EA916 : 0EBF16 0EE816 : 0EE616 0EF716 0F2816 0F2916 : 0F3F16 0F6816 : 0F7616 0F7716 0FA816 0FA916 : 0FBF16 0FE816 : 0FF616 0FF716
Block 13
Block 14
Block 15
Block 16
82
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Display sequence RAM address order Display sequence RAM address order
1 1
2 2
3 4
4 5
5 7
6 8
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
1.5Tc size
10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32 34 35 37 38 40 block
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40
1Tc size
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 block
Fig. 81. RAM Data for 3nth Character
Note: Do not read from and write to addresses shown in Table 14.
Table 14. List of Access Disable Addresses 087816 08F816 097816 09F816 0A7816 0AF816 0B7816 0BF816 0C7816 0CF816 0D7816 0DF816 0E7816 0EF816 0F7816 0FF816 087916 08F916 097916 09F916 0A7916 0AF916 0B7916 0BF916 0C7916 0CF916 0D7916 0DF916 0E7916 0EF916 0F7916 0FF916 087A16 08FA16 097A16 09FA16 0A7A16 0AFA16 0B7A16 0BFA16 0C7A16 0CFA16 0D7A16 0DFA16 0E7A16 0EFA16 0F7A16 0FFA16
83
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Blocks 1 to16 b7 RF7 RF6 RF5 RF4 RF3 RF2 b0 b7 b0 b3 b0
RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 RC23 RC22 RC21 RC20
Character code
Color code 1
Color code 2
CC mode Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC20 RC21 RC22 RC23 Not used Not used 0 Control of character color R Control of character color G Control of character color B OUT1 control Flash control Underline control Italic control Control of background color R Control of background color G Control of background color B 0: Character output 1: Background output 0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON 0: Italic OFF 1: Italic ON Not used
0: Color signal output OFF 1: Color signal output ON
OSD mode Function Bit name Function
EXOSD mode Bit name Function
Bit name
Character code (Low-order 8 bits)
Specification of character code in OSD ROM
Character code (Low-order 8 bits)
Specification of character code in OSD ROM
Character code (Low-order 8 bits)
Specification of character code in OSD ROM
0 Control of character color R Control of character color G Control of character color B OUT1 control 0: Character output 1: Background output
0: Color signal output OFF 1: Color signal output ON
0 Character color code 0 (CC0) Character color code 1 (CC1) Character color code 2 (CC2) OUT1 control Extra code 0 Extra code 1 Extra code 2 (EX2)
0: Color signal output OFF Background color code 0 1: Color signal output ON
Specification of character color
0: Character output 1: Background output Specification of
(EX0) extra code in OSD ROM (EX1)
0: Color signal output OFF Control of background 1: Color signal output ON
Specification of
color R Control of background color G Control of background color B
(BCC0) background color Background color code 1 (BCC1) Background color code 2 (BCC2) Extra code 3 Specification of (EX3) extra code in OSD ROM
Notes 1: Read value of bits 4 to 7 of the color code 2 is undefined. 2: For "not used" bits, the write value is read. 3: Set "0" to RC10.
Fig. 82. Structure of OSD RAM
84
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(7) Character color
The color for each character is displayed by the color code 1. The kinds and specification method of character color are different depending on each mode. CC mode .................. 7 kinds Specified by bits 1 (R), 2 (G), and 3 (B) of color code 1 OSD mode ............... 7 kinds Specified by bits 1 (R), 2 (G) and 3 (B)of color code 1 EXOSD mode .......... 5 kinds Specified by bits 1 (CC0), 2 (CC1), and 3 (CC2) of color code 1 The correspondence Table of color code 1 and color signal output in the EXOSD mode is shown in Table 15.
Table 15. Correspondence Table of Color Code 1 and Color Signal Output in EXOSD Mode Color Code 1 Bit 3 CC2 0 0 0 0 1 1 1 1 Bit 2 CC1 0 0 1 1 0 0 1 1 Bit 1 CC0 0 1 0 1 0 1 0 1 R 0 1 0 1 1 1 0 1 Color Signal Output G 0 0 1 1 1 1 1 1 B 0 0 0 0 0 1 1 1
* * *
(8) Character background color
The character background color can be displayed in the character display area. The character background color for each character is specified by color code 2. The kinds and specification method of character background color are different depending on each mode. CC mode .................. 7 kinds Specified by bits 0 (R), 1 (G), and 2 (B) of color code 2 OSD mode ............... 7 kinds Specified by bits 0 (R), 1 (G), and 2 (B) of color code 2 EXOSD mode .......... 5 kinds Specified by bits 0 (BCC0), 1 (BCC1), and 2 (BCC2) of color code 2 The correspondence table of the color code 2 and color signal output in the EXOSD mode is shown in Table 16.
* * *
Table 16. Correspondence Table of Color Code 2 and Color Signal Output in EXOSD Mode Color Code 2 Bit 2 BCC2 0 0 0 0 1 1 1 1 Bit 1 BCC1 0 0 1 1 0 0 1 1 Bit 0 BCC0 0 1 0 1 0 1 0 1 R 0 1 0 1 1 1 0 1 Color Signal Output G 0 0 1 1 1 1 1 1 B 0 0 0 0 0 1 1 1
Note : The character background color is displayed in the following part : (character display area)-(character font)-(border)-(extra font). Accordingly, the character background color does not mix with these color signal.
85
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(9) OUT1, OUT2 signals
The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by bit 4 of color code 1 (refer to Figure 82), bits 2 and 7 of
the block control register i (refer to Figure 65). The setting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 83.
Block control register i OUT2 output control bit (b7) Border output control bit (b2)
OUT1 control (b4 of color code 1)
Output waveform
0 0 1 0 0 1 1
OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2
0 0 1 1 0 1
OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1
1
OUT2
Fig. 83. Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
86
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(10) Attribute
The attributes (flash, underline, italic) are controlled to the character font. The attributes for each character are specified by the color codes 1 and 2 (refer to Figure 71). The attributes to be controlled are different depending on each mode. CC mode ..................... Flash, underline, italic OSD mode .................. Border (all bordered, shadow bordered can be selected) EXOSD mode ............. Border (all bordered, shadow bordered can be selected) , extra font (16 kinds) 1 Under line The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by bit 6 of color code 1. The color of underline is the same color as that of the character font. 2 Flash The parts of the character font, the underline, and the character background are flashed only in the CC mode. The color signals (R, G, B, OUT1) of the character font and the underline are controlled by bit 5 of color code 1. All of the color signals for the character font flash. However, the color signal for the character background can be controlled by bit 3 of the OSD control register (refer to Figure 64). The flash cycle bases on the VSYNC count. * VSYNC cycle 5 48 ; 800 ms (at flash ON) * VSYNC cycle 5 16 ; 267 ms (at flash OFF) 3 Italic The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic is controlled by bit 7 of color code 1. The display example of the italic and underline is shown in Figure 85. In this case, "R" is displayed. Notes 1: When setting both the italic and the flash, the italic character flashes. 2: When the pre-divide ratio = 1, the italic character with slant of 1 dot 5 5 steps is displayed (refer to Figure 84 (c)). When the pre-divide ratio = 2, the italic character with slant of 1/2 dot 5 10 steps is displayed (refer to Figure 84 (d)). 3: The boundary of character color is displayed in italic. However, the boundary of character background color is not affected by the italic (refer to Figure 85). 4: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 85). 5: When displaying the italic character in the block with the pre-divide ratio = 1, set the OSD clock frequency to 11 MHz to 14 MHz.
87
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Color code 1
Color code 1
Bit 6
Bit 7
Bit 6
Bit 7
0
0
1
0
(a) Ordinary
(b) Underline
Color code 1 Bit 6 Bit 7
Color code 1
Bit 6
Bit 7
0
1
0
1
(c) Italic (pre-divide ratio = 1)
(d) Italic (pre-divide ratio = 2)
Fig. 84. Example of Attribute Display (in CC mode)
Italic on one side
Italic on both sides
Bit 7 of color code 1
1
0
0
1
1
0
1
Note : The wavy-lined is the boundary of character color
Fig. 85. Example of Italic Display
88
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Extra font There are 16 kinds of the extra fonts configured with 16 ! 26 dots in OSD ROM. This 16 kinds fonts can be displayed by ORed with the character font by a character unit (refer to Figure 62). In only the EXOSD mode, the extra font is controlled the following : bits 7 to 5 of the color code 1 and bit 3 of the color code 2. The extra font color for each screen is specified by the extra color register. When the character font overlaps with the extra font, the color of the area becomes the ORed color of both fonts.
Notes 1 : When using the extra font, set bits 7 and 6 of the OSD control register to "0" (refer to Figure 64). 2 : Extra fonts are always displayed by ORed with the character font. Accordingly, when displaying only a extra font, set a blank for a character font and OR with it.
Extra Font Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Extra font color register (EC) [Address 021916] B 0 1 2 Name Extra font color R control bit (EC0) Extra font color G control bit (EC1) Extra font color B control bit (EC2) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset 0 0 0 0 0 RW RW RW RW RW R--
3, 4 Fix these bits to "0." Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
5 to 7
Fig. 86. Extra Font Color Register
16 dots 16 dots
16 dots
20 dots
Blank character font
Fig. 87. Display Example of Only Extra Font
26 dots
Extra font specified by EX0 to EX3
26 dots
+ (OR)
89
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Border The border is output in the OSD mode and the EXOSD mode. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure 88) by bit 2 of the OSD control register (refer to Figure 64). The border ON/OFF is controlled by bit 2 of the block control register (refer to Figure 65). The OUT1 signal is used for border output. The border color for each screen is specified by the border color register. The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of the character font dot size. However, only when the pre-divide ratio = 2 and character size = 1.5TC, the horizontal size is 1.5TC. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font.
Notes 1 : There is no border for the extra font. 2 : The border dot area is the shaded area as shown in Figure 90. In the EXOSD mode, top and bottom of character font display area is not bordered. 3 : When the border dot overlaps on the next character font, the character font has priority (refer to Figure 91 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 91 B). 4 : The border is not displayed at right side of the most right dot in the display area of the 40th character (the character located at the most right of the block). However, note that MASK version cannot display the border for the right edge dots of the 36th's character area.
All bordered
Fig. 88. Example of Border Display
Shadow bordered
y
x
Scan mode Border dot size Vertical dot size of character font Horizontal size (x) Vertical size (y) Normal scan mode Bi-scan mode
1/2H
1H, 2H, 3H
1/2H, 1H, 2H, 3H
1TC (OSD clock cycle divided in pre-divide circuit) 1.5TC when selecting 1.5TC for character size.
1/2H
1H
1H
Fig. 89. Horizontal and Vertical Size of Border
90
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD mode
EXOSD mode
16 dots
16 dots
Character font area
Character font area
1 dot width of border
20 dots
1 dot width of border 1 dot width of border 1 dot width of border
Fig. 90. Border Area
Character boundary B
Character boundary A
Fig. 91. Border Priority
20 dots
Character boundary B
91
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Border Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Border color register (FC) [Address 021B16] B 0 1 2 Name Border color R control bit (FC0) Border color G control bit (FC1) Border color B control bit (FC2) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset 0 0 0 0 0 RW RW RW RW RW R--
3, 4 Fix these bits to "0." Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
5 to 7
Fig. 92. Border Color Register
92
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(11) Multiline Display
The M37274EFSP can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. The mode in which an OSD interrupt occurs is different depending on the setting of the raster color register (refer to Figure 99). * When bit 7 of the raster color register is "0" An OSD interrupt occurs at the end of block display in the OSD and the EXOSD mode. * When bit 7 of the raster color register is "1" An OSD interrupt occurs at the end of block display in the CC mode.
Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register (addresses 00D016 to 00DB16), an OSD interrupt request does not occur (refer to Figure 93 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 93 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 93 (C)).
Block 1 (on display) Block 2 (on display) Block 3 (on display) Block 4 (on display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
Block 1 (on display) Block 2 (on display) Block 3 (off display) Block 4 (off display)
"OSD interrupt request" "OSD interrupt request" No "OSD interrupt request" No "OSD interrupt request"
On display (OSD interrupt request occurs at the end of block display) (A)
Off display (OSD interrupt request does not occur at the end of block display)
Block 1 "OSD interrupt request" Block 1 Block 2
No "OSD interrupt request" "OSD interrupt request"
Block 2 "OSD interrupt request" Block 3 "OSD interrupt request"
Window In CC mode (B) (C)
Fig. 93. Note on Occurence of OSD Interrupt
93
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(12) Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : * the character area except character code "0916 " * the character area on the left and right sides This function is turned on and off by bit 4 of the OSD control register (refer to Figure 64).
Note : When using this function, set "0916" to the character below : * The 1st character * The 34th character and the following character.
Table 17. Setting for Automatic Solid Space Bit 4 of OSD control register Bit 7 of block control register Bit 4 of color code 1 OUT1 output signal 0 Character font part OUT2 output signal OFF 0 1 Character display area OFF Character display area OFF Solid space 0 Character font part 0 1 1 0 Solid space 0 1 0 Character font part 1 1 1
When setting the character code "05 16" as the character A, "06 16" as the character B.
(OSD RAM) Character to be displayed
09 05 09 09 09 06 06
16 16 16 16 16 16 16
***
06 09 09
16 16 16
***
09
16
(Display screen)
***
***
1st 2nd 3rd character character character
No blank output
34th character
35th character
40th character
(See note 1)
(See note 1)
Fig. 94. Display Screen Example of Automatic Solid Space
94
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(13) Scan Mode
M37274EFSP has the bi-scan mode for corresponding to HSYNC of double speed frequency. In the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. The scan mode is selected by bit 1 of the OSD control register (refer to Figure 64).
Table 18. Setting for Scan Mode Parameter Bit 1 of OSD control register Vertical display start position Vertical dot size Scan Mode Normal Scan 0 Value of vertical position register ! 1H 1TC ! 1/2H 1TC ! 1H 2TC ! 2H 3TC ! 3H Bi-Scan 1 Value of vertical position register ! 2H 1TC ! 1H 1TC ! 2H 2TC ! 4H 3TC ! 6H
(14) Window Function
This function sets the top and bottom boundary of display limit on a screen. The window function is valid only in the CC mode. The top boundary is set by window H registers 1 and 2. The bottom boundary is set by window L registers 1 and 2. This function is turned on and off by bit 5 of the OSD control register (refer to Figure 64). The window H registers 1 and 2 is shown in Figures 96 and 97, of window L registers 1 and 2 is shown in Figures 98 and 99.
Notes 1: Set values except "0016" and "0116" to the window H register 1 when the window H register 2 is "0016." 2: Set the register value fit for the following condition : (WH1 + WH2) < (WL1 + WL2)
ABCDE F GH I J
EXOSD mode
Top boundary of window
CC mode CC mode CC mode Window
KL
MNO
PQRST UV WX Y
Screen
OSD mode
Bottom boundary of window
Fig. 95. Example of Window Function
95
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Window H Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Window H register 1 (WH1) [Address 021C16] B Name Functions After reset RW
0 Control bits of window to top boundary 7 (WN10 to WN17) (See note 1)
Top boundary position (low-order 8 bits) Indeterminate R W TH ! (setting value of low-order 2 bits of WH2 ! 162 + setting value of high-order 4 bits of WH1 ! 161 + setting value of low-order 4 bits of WH1 ! 160)
Notes 1: Set values except "00 16" to the WH1 when WH2 is "00 16." 2: TH is cycle of HSYNC. 3: WH2: Window H register 2
Fig. 96. Window H Register 1
Window H Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Window H register 2 (WH2) [Address 021E16] B Name Functions After reset RW
0, 1 Control bits of window top boundary (WN20 ,WN21) (See note 1)
Top boundary position (high-order 2 bits) Indeterminate R W TH ! (setting value of low-order 2 bits of WH2 ! 162 + setting value of high-order 4 bits of WH1 ! 161 + setting value of low-order 4 bits of WH1 ! 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Set values except "00 16" to the WH1 when WH2 is "00 16." 2: TH is cycle of HSYNC. 3: WH1: Window H register 1
Fig. 97. Window H Register 2
96
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Window L Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Window L register 1 (WL1) [Address 021D16] B Name Functions After reset RW
0 Control bits of window to top boundary 7 (WL10 to WL17) (See note 1)
Indeterminate R W Top boundary position (low-order 8 bits) TH ! (setting value of low-order 2 bits of WL2 ! 162 + setting value of high-order 4 bits of WL1 ! 161 + setting value of low-order 4 bits of WL1 ! 160)
Notes 1: Set values fit for the following condition: (WH1+WH2 !162)<(WL1+WL2! 162) 2: TH is cycle of HSYNC. 3: WL2: Window L register 2
Fig. 98. Window L Register 1
Window L Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Window L register 2 (WL2) [Address 021F16] B Name Functions After reset RW
0, 1 Control bits of window top boundary (WL20, WL21) (See note 1)
Top boundary position (high-order 2 bits) Indeterminate R W TH ! (setting value of low-order 2 bits of WL2 ! 162 + setting value of high-order 4 bits of WL1 ! 161 + setting value of low-order 4 bits of WL1 ! 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Set values fit for the following condition: (WH1+WH2 !162)<(WL1+WL2! 162) 2: TH is cycle of HSYNC. 3: WL1: Window L register 1
Fig. 99. Window L Register 2
97
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(15) OSD Output Pin Control
The OSD output pins R, G, B, and OUT1 can also function as ports P52, P53, P54 and P55. Set the corresponding bit of the OSD port control register (address 00CB16) to "0" to specify these pins as OSD output pins, or set it to "1" to specify it as a general-purpose port P5 pins. The OUT2 can also function as port P10. Set the corresponding bit of the port P1 direction register (address 00C316) to "1" (output mode). After that, switch between the OSD output function and the port function by the OSD port control register. Set the corresponding bit to "1" to specify the pin as OSD output pin, or set it to "0" to specify as port P1 pin. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the I/O polarity control register (address 021716) . Set a bit to "0" to specify positive polarity; set it to "1" to specify negative polarity (refer to Figure 78). The OSD port control register is shown in Figure 100.
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 OSD port control register (PF) [Address 00CB16]
B
Name
Functions
After reset R W 0 RW RW RW RW RW RW
0, 1, Fix these bits to "0." 7 2 3 4 5 6 Port P52 output signal selection bit (R) Port P53 output signal selection bit (G) Port P54 output signal selection bit (B) Port P55 output signal selection bit (OUT1) Port P10 output signal selection bit (OUT2) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 0 : Port P10 output 1 : OUT2 signal output (Note)
0
0 0 0 0
Note. Set bit 0 of Port P1 direction register (address 00C3 16) to "1" (output mode).
Fig. 100. OSD Port Control Register
98
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
(16) Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 7 raster colors can be obtained. If the OUT1 pin has been set to raster coloring output, a raster coloring signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, and B pins have been set to output, a raster coloring signal is output in the part except a no-raster colored character (in Figure 102, a character "1") and the character background output during 1 horizontal scanning period. This ensures that the character color/the character background color is not mixed with the raster color. The structure of the raster color register is shown in Figure 101, the example of raster coloring is shown in Figure 102.
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Raster color register (RC) [Address 021816] B 0 1 2 Name Raster color R control bit (RC0) Raster color G control bit (RC1) Raster color B control bit (RC2) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset R W 0 0 0 0 0 : No output 1 : Output 0 : No output 1 : Output 0 : Interrupt occurs at end of OSD or EXOSD block display 1 : Interrupt occurs at end of CC mode block display 0 0 0 RW RW RW R-- RW RW RW
3, 4 Fix these bits to "0." 5 Raster color OUT1 control bit (RC5)
6 Raster color OUT2 control bit (RC6) 7 OSD interrupt source selection bit (RC7)
Fig. 101. Raster Color Register
99
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
: Character color "RED" (R) : Border color "GREEN" (G) : Background color "MAGENTA" (R and B) : Raster color "BLUE" (B and OUT1)
A
A'
HSYNC OUT1 R G B
Signals across A-A'
Fig. 102. Example of Raster Coloring
100
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes ! 2 blocks. Block 1 : addresses 02C016 to 02DF16 Block 2 : addresses 02E016 to 02FF16 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. When the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. The ROM correction function is controlled by the ROM correction enable register. Notes 1 : Specify the first address (op code address) of each instruction as the ROM correction address. 2 : Use the JMP instruction (total of 3 bytes) to return from the main program to the correction program. 3 : Do not set the same ROM correction address to blocks 1 and 2.
ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order)
024216 024316 024416 024516
Fig. 103. ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0
ROM correction enable register (RCR) [Address 024616] B
0 1
Name
Block 1 enable bit (RC0) Block 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0
RW RW RW R--
2, 3 Fix these bits to "0."
0
4 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
Fig. 104. ROM Correction Enable Register
101
P
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament ic Not e par Som
REL
A IMIN
RY
MITSUBISHI MICROCOMPUTERS
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V 10 %, hold the ______ RESET pin at LOW for 2 s or more, then return is to HIGH. Then, as shown in Figure 106, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 5 to 9. An example of the reset circuit is shown in Figure 105. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V.
Poweron 4.5 V Power source voltage 0 V
Reset input voltage 0 V
0.9 V
27 1 5
M51953AL
Vcc
30
RESET
4 3 0.1 F 26
Vss
M37274EFSP
Fig. 105. Example of Reset Circuit
XIN RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) ? ? ? ?
01, S
01, S-1 01, S-2
FFFE
FFFF
ADH, ADL
Reset address from the vector table ? ? ? ADL ADH
Notes 1 : f(XIN) and f( ) are in the relation : f(XIN) = 2*f (). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, "FF 16" is set in timer 3 and "0716" is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.
Fig. 106. Reset Sequence
102
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
CLOCK GENERATING CIRCUIT
The M37274EFSP has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock, clear bits 5 and 4 of the clock source control register to "0." To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to "1."
(3) Low-Speed Mode
If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to "1." When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption. To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to "0." At reset, this bit is set to "1" and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to "1" by software before executing.
M37274EFSP
Oscillation Control (1) Stop mode
The built-in clock generating circuit is shown in Figure 95. When the STP instruction is executed, the internal clock stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and "FF16" is set in timer 3 and "0716" is set in timer 4. Select f(XIN)/16 or f(XCIN)/ 16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to "0" before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock keeps its "H" level until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used.
XCIN
Rf
XCOUT
XIN
XOUT
Rd
CCIN
CCOUT
CIN
COUT
Fig. 107. Ceramic Resonator Circuit Example
(2) Wait mode
M37274EFSP XCIN XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss
When the WIT instruction is executed, the internal clock stops in the "H" level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) VSYNC interrupt (2) OSD interrupt (3) Timers 1 and 2 interrupts using TIM2 pin input as count source (4) Timer 3 interrupt using TIM3 pin input as count source (5) Data slicer interrupt (6) Multi-master I2C-BUS interface interrupt (7) f(XIN)/4096 interrupt (8) All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source (9) All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source (10) A-D conversion interrupt
Fig. 108. External Clock Input Circuit Example
103
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
XCIN
XCOUT
XIN
OSC1 oscillating mode selection bits (Notes 1, 4) XOUT "1" 1/2 "0" Internal system clock selection bit (Notes 1, 3) 1/8 "1" "0"
Timer 3 count stop bit (Notes 1, 2) Timer 3
Timer 4 count stop bit (Notes 1, 2) Timer 4
Timer 3 count source selection bit (Notes 1, 2) Timing (Internal clock)
Main clock (XIN-XOUT) stop bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Q S S Q Q S
Reset STP instruction
R
STP instruction
WIT instruction
R
R
Reset Interrupt disable flag I Interrupt request
Notes 1 : The value at reset is "0." 2 : Refer to the structure of timer mode register 2. 3 : Refer to the structure of CPU mode register (next page). 4 : Refer to the structure of clock source control register.
Fig. 109. Clock Generating Circuit Block Diagram
104
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Reset
High-speed operation start mode
WIT instruction 8MHz oscillating 32kHz oscillating is stopped (HIGH) Timer operating Interrupt External INT, timer interrupt, or SI/O interrupt 8MHz oscillating 32kHz oscillating f() = 4MHz
STP instruction 8MHz stopped 32kHz stopped is stopped (HIGH) Interrupt (Note 1) External INT CM7 = 0
CM7 = 1
WIT instruction 8MHz oscillating 32kHz oscillating is stopped (HIGH) Timer operating (Note 3) 8MHz oscillating 32kHz oscillating f() = 16kHz Interrupt
STP instruction 8MHz stopped 32kHz stopped is stopped (HIGH) Interrupt (Note 2)
CM6 = 0 The program must allow time for 8MHz oscillation to stabilize
CM6 = 1
8MHz stopped 32kHz oscillating is stopped (HIGH) Timer operating (Note 3)
WIT instruction 8MHz stopped 32kHz oscillating f() = 16kHz Interrupt
STP instruction 8MHz stopped 32kHz stopped = stopped (HIGH ) Interrupt (Note 2)
CPU mode register (Address : 00FB16) CM6 : Main clock (X IN-XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X CIN pin. The indicates the internal clock.
Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock divided by 8 is used as the timer count source, the frequency of the count source is 2kHz.
Fig. 110. State Transitions of System Clock
105
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
DISPLAY OSCILLATION CIRCUIT
The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 4 of the clock source control register (address 021616).
ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User's Manual for details.
MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 User's Manual for details.
PROGRAMMING NOTES
(1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor ( 0.1 mF) directly between the VCC pin-VSS pin, AVCC pin-VSS pin, and the VCC pin-CNVSS pin, using a thick wire.
OSC1
OSC2
L C1 C2
Fig. 111. Display Oscillation Circuit
AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will oper______ ate by connecting the following circuit to the RESET pin.
Circuit example 1
Vcc
RESET
Vss
Circuit example 2
RESET
Vcc
Vss
Note : Make the level change from "L" to "H" at the point at which the power source voltage exceeds the specified voltage.
Fig. 112. Auto-clear Circuit Example
106
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PROM Programming Method
The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37274EFSP Name of Programming Adapter PCA7400
The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 97 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution : The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 hours.
Fig. 113. Programming and testing of One Time PROM version
107
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC, AVCC VI VI Input voltage Input voltage Parameter Power source voltage VCC, AVCC CNVSS P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P64, P63, P70-P72, XIN, HSYNC, VSYNC, ______ RESET P03, P10-P17, P20-P27, P30, P31, P52-P55, SOUT, SCLK, XOUT, OSC2 P00-P02, P04-P07 P52-P55, P10, P03, P15-P17, P20-P27, P30, P31 P52-P55, P10, , P03, P15-P17, P20-P27, SOUT, SCLK P11-P14 P00-P02, P04-P07 P30, P31 Ta = 25 C Conditions All voltages are based on VSS. Output transistors are cut off. Ratings -0.3 to 6 -0.3 to 6 -0.3 to VCC + 0.3 Unit V V V
VO
Output voltage
-0.3 to VCC + 0.3
V
VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg
Output voltage Circuit current Circuit current Circuit current Circuit current Circuit current
-0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 6 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 -10 to 70 -40 to 125
V mA mA mA mA mA mW C C
Power dissipation Operating temperature Storage temperature
RECOMMENDED OPERATING CONDITIONS (Ta = -10 C to 70 C, VCC = 5 V 10 %, unless otherwise noted)
Symbol VCC, AVCC VCC, AVCC VSS VIH1 Parameter Power source voltage (Note 4), During CPU, OSD, data slicer operation RAM hold voltage (when clock is stopped) Power source voltage HIGH input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P64, P70-P72, HSYNC, VSYNC, ______ RESET, XIN, P63 HIGH input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage P00-P07, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64, P70-P72 LOW input voltage SCL1, SCL2, SDA1, SDA2 ______ LOW input voltage (Note 6) RESET, XIN, OSC1, HSYNC, VSYNC, INT1, INT2, INT3, TIM2, TIM3, SCLK, SIN HIGH average output current (Note 1) P52-P55, P10, P03, P15-P17, P20-P27, P30, P31 LOW average output current (Note 2) P52-P55, P10, P03, P15-P17, P20-P27, SOUT, SCLK LOW average output current (Note 2) P11-P14 LOW average output current (Note 2) P00-P02, P04-P07 LOW average output current (Note 3) P30, P31 Oscillation frequency (for CPU operation) (Note 5) Oscillation frequency (for sub-clock operation) Oscillation frequency (for OSD) Input frequency Input frequency Input frequency Input frequency Input amplitude video signal OSC1 XIN XCIN 7.9 29 11.0 26.5 8.0 32 27.0 Min. 4.5 2.0 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 5.5 0 VCC Unit V V V V
VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) f(XCIN) fOSC fhs1 fhs2 fhs3 fhs4 VI
0.7VCC 0 0 0
VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 1 10 8.1 35 27.0 27.5 100 1 400 16.206 2.5
V V V V mA mA mA mA mA MHz kHz MHz kHz MHz kHz kHz V
LC oscillating mode Ceramic oscillating mode TIM2, TIM3, INT1, INT2, INT3 SCLK SCL1, SCL2 Horizontal sync. signal of video signal CVIN
15.262 1.5
15.734 2.0
108
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ELECTRIC CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted)
Symbol ICC Parameter Power source current System operation Test conditions VCC = 5.5 V, CRT OFF f(XIN) = 8 MHz Data slicer OFF CRT ON Data slicer ON VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Wait mode VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM5 = "0", CM6 = "1") Stop mode VOH VOL HIGH output voltage P52-P55, P10, P03, P15-P17, P20-P27, P30, P31 LOW output voltage P52-P55, P10, SOUT, SCLK, P00-P07, P15-P17, P20-P27 LOW output voltage P30, P31 LOW output voltage P11-P14 VT+-VT-
______
Limits Min. Typ. 15 30 60 Max. 30
Unit
mA 50 200
A
2 25
4 100
mA
A
1 2.4 0.4 3.0 V 0.4 0.6 0.5 1.3 V 10 V
VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = -0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V IOL = 3 mA IOL = 6 mA VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 12 V
IIZH
Hysteresis (Note 6) RESET, HSYNC, VSYNC, INT1, INT2, INT3, TIM2, TIM3, SIN, SCLK, SCL1, SCL2, SDA1, SDA2 ______ HIGH input leak current RESET, P03, P10-P17, P20-P27, P30, P31, P40-P46, P63, P64, P70-P72, HSYNC, VSYNC HIGH input leak current P00-P02, P04-P07
______
5
A
10 5 130
IIZL
LOW input leak current
RESET, P00-P07, P10-P17, P20- VCC = 5.5 V VI = 0 V P27, P30, P31, P40-P46, P63, P64, P70-P72, HSYNC, VSYNC VCC = 4.5 V
A
RBS
I2C-BUS*BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2)
Notes 1: 2: 3: 4:
5: 6:
7: 8:
The total current that flows out of the IC must be 20 or less. The total input current to IC (IOL1 + IOL2 + IOL3) must be 20 mA or less. The total average input current for ports P30, P31 to IC must be 10 mA or less. Connect 0.1 F or more capacitor externally between the power source pins VCC-VSS and AVCC-VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally between the pins VCC-CNVSS. Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. P16, P41-P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P17 and P46 have the hysteresis when these pins are used as serial I/O pins. When using the sub-clock, set fCLK < fCPU/3. Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports * When the same limits: I/O port name. * When the limits of functins except ports are different from I/O port limits: function pin name.
109
PR
. nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER CHARACTERISTICS
Symbol -- -- -- VOT VFST TCONV VREF RLADDER VIA Resolution Non-linearity error Differential non-linearity error Zero transition error Full-scale transition error Conversion time Reference voltage Ladder resistor Analog input current Parameter
(VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted) Test conditions Limits Min. 0 0 VCC = 5.12V IOL (SUM) = 0mA VCC = 5.12V 0 0 12.25 Typ. Max. 8 2 0.9 2 4 12.5 VCC 25 0 VREF Unit bits LSB LSB LSB LSB
s
V k V
MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Symbol tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition 250 4.7 4.0 0 4.0 300 Parameter Standard clock mode High-speed clock mode Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit
s s s
ns
s s
ns ns
s s
Note: Cb = total capacitance of 1 bus line
SDA tHD:STA tSU:STO
tBUF tLOW P SCL S
tR
tF Sr P
tHD:STA
tHD:DAT
tHIGH
tSU:DAT
tSU:STA
S : Start condition Sr : Restart condition P : Stop condition
Fig. 114. Definition Diagram of Timing on Multi-master I2C-BUS
110
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PACKAGE OUTLINE
111
PR
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
IN LIM E
ARY
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
52P4B (52-PIN SHRINK DIP) MARK SPECIFICATION FORM
112
MITSUBISHI MICROCOMPUTERS
n. ange atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PRE
L
R INA IM
Y
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
APPENDIX Pin Configuration (TOP VIEW)
HSYNC VSYNC P40/AD4 P41/INT2 P42/TIM2 P43/TIM3 P24/AD3 P25/AD2 P26/AD1 P27/AD5 P00/PWM4 P01/PWM5 P02/PWM6 P17/SIN P44/INT1 P45/SOUT P46/SCLK AVCC HLF/AD6 P72/RVCO P71/VHOLD P70/CVIN CNVSS XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10
52 51 50 49 48 47 46 45 44 43
P52/R P53/G P54/B P55/OUT1 P04/PWM0 P05/PWM1 P06/PWM2 P07/PWM3 P20 P21 P22 P23 P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15 P16/INT3 P03/DA P30 P31 RESET P64/OSC2/XCOUT P63/OSC1/XCIN VCC
M37274EFSP
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Outline 52P4B
113
MITSUBISHI MICROCOMPUTERS
. e tion ang ifica t to ch pec c al s subje fin re a ot a is n limits his ic e: T ament otic par N e Som
P
REL
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Memory Map
000016 Zero page SFR1 area
1000016 1080016
Not used
RAM (1024 bytes)
00C016 00FF16 010016 020016 024816 02C016 02FF16 030016 053F16
SFR2 area Not used ROM correction memory Block 1 : addresses 02C0 16 to 02DF16 Block 2 : addresses 02E0 16 to 02FF16 ROM for OSD (11072 bytes) Not used
155FF16 Not used 1800016
RAM for OSD (Note) (1920 bytes)
080016 0FF716 Not used 100016
ROM (60 K bytes) 1E41F16 FF0016 FFDE16 FFFF16
Interrupt vector area
Not used 1FFFF16 Special page
Note : Refer to Table 13. Contents of OSD RAM.
114
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Memory Map of Special Function Register (SFR)
sSFR1 area (addresses C016 to DF16)
< Bit allocation >
:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register
b7 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) OSD port control register (PF) Port P6 (P6) Port P7 (P7) OSD control register (OC)
P6IM T3SC
Bit allocation
State immediately after reset
b0 b7 b0
P46D P45D
0 B G R 0 0 0 0 0
0
OUT2 OUT1
OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 HP2 HP1 HP0 BC12 BC 11 BC10 BC22 BC 21 BC20 BC32 BC 31 BC30
Horizontal position register (HP) HP7 HP6 HP5 HP4 HP3 Block control register 1 (BC1) BC17 BC16 BC 15 BC14 BC 13 Block control register 2 (BC2) BC27 BC26 BC 25 BC24 BC 23 Block control register 3 (BC3) BC37 BC36 BC 35 BC34 BC 33 Block control register 4 (BC4) Block control register 5 (BC5) Block control register 6 (BC6) Block control register 7 (BC7) Block control register 8 (BC8) Block control register 9 (BC9) Block control register 10 (BC10) Block control register 11 (BC11) Block control register 12 (BC12) Block control register 13 (BC13) Block control register 14 (BC14) Block control register 15 (BC15) Block control register 16 (BC16)
BC47 BC46 BC 45 BC44 BC 43 BC42 BC 41 BC40 BC57 BC56 BC 55 BC54 BC 53 BC52 BC 51 BC50 BC67 BC66 BC 65 BC64 BC 63 BC62 BC 61 BC60 BC77 BC76 BC 75 BC74 BC 73 BC72 BC 71 BC70 BC87 BC86 BC 85 BC84 BC 83 BC82 BC 81 BC80 BC97 BC96 BC 95 BC94 BC 93 BC92 BC 91 BC90
BC107 BC106 BC105 BC104 BC103 BC102 BC101 BC100 BC117 BC116 BC115 BC114 BC113 BC112 BC111 BC110 BC127 BC126 BC125 BC124 BC123 BC122 BC121 BC120 BC137 BC136 BC135 BC134 BC133 BC132 BC131 BC 130 BC147 BC146 BC145 BC144 BC143 BC142 BC141 BC140 BC157 BC156 BC155 BC154 BC153 BC152 BC151 BC150 BC167 BC166 BC165 BC164 BC163 BC162 BC161 BC160
? 0016 ? 0016 ? 0016 ? 0016 ? 0016 ? 0016 ? 00 0016 0016 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
?
?
?
115
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
sSFR1 area (addresses E016 to FF16)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register
b7
Bit allocation 1 0
SSL7
State immediately after reset
b0
Caption position register (CP) Start bit position register (SP) Window register (WN) Sync slice register (SSL)
Caption data register 1 (CD1) Caption data register 2 (CD2)
0
b0 b7 0 CP4 CP3 CP2 CP1 CP0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0 WN5 WN4 WN3 WN2 WN1 WN0 0000101
Clock run-in register 1 (CR1) Clock run-in register 2 (CR2)
Clock run-in detect register 1 (CRD1) Clock run-in detect register 2 (CRD2) Data slicer control register 1 (DSC1) Data slicer control register 2 (DSC2) Caption data register 3 (CD3) Caption data register 4 (CD4)
0 1
1 0
0 0
1 1
CR13 CR12 CR11 CR10
1
1
CR21
1
CRD17 CRD15 CRD15 CRD15 CRD15 CRD27 CRD25 CRD25 CRD25 CRD25 CRD22 CRD21 CRD20 DSC17 DSC27
0 0
DSC15 DSC25
0 0
0 0
DSC12 DSC11 DSC10 DSC22 DSC21 DSC20
? ?
0 0
? ?
A-D conversion register (AD) A-D control register (ADCON) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
0
0
ADVREF ADSTR
ADIN2 ADIN1 ADIN0
0
?
0
TM17 TM16 TM15 TM14 TM13 TM12 TM11 TM10 TM27 TM26 TM25 TM24 TM23 TM22 TM21 TM20 D7 D6 D5 D4 D3 D2 D1 D0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB
0
0
0
BSEL1 BSEL0 10 BIT ALS ES0 BC2 BC1 BC0 SAD ACK FAST ACK BIT CCR4 CCR3 CCR2 CCR1 CCR0 MODE
CM7 CM6 CM5
1
1
CM2
0
0
0
0
1
ADR VSCR CRTR TM4R TM3R TM2R TM1R
0
T56R IICR INT2R 1MSR SIOR DSR INT1R CK0 ADE VSCE CRTE TM4E TM3E TM2E TM1E
T56S T56E IICE INT2E 1MSE SIOE DSE INT1E
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00 00 0016 0016 ? 01 FF16 0716 FF16 0716 0016 0016 ? 0016 10 0016 0016 11 0016 0016 0016 0016
0 ?
0 0
0 0
0
0
0
0
0
?
1
0
0
116
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
sSFR2 area (addresses 20016 to 21F16)

:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 Register
b7 PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM5 register (PWM5) PWM6 register (PWM6) Clock run-in detect register 3 (CRD3) CRD35 CRD34 CRD33 CRD32 CRD31 Clock run-in register (CR3) PWM mode register 1 (PN) PWM mode register 2 (PW) Timer 5 (TM5) Timer 6 (TM6)
CR36 CR35 CR34 CR33 CR32 CR31 CR30
Bit allocation
b0 b7
State immediately after reset
b0
PN3 PN2 PN1 PN0 0 PW6 PW5 PW4 PW3 PW2 PW1 PW0
?
?
?
0016
Sync pulse counter register (SYC) Data slicer control register 3 (DSC3) Interrupt input polarity register (IP) Serial I/O mode register (SM) Serial I/O register (SIO) Clock source control register (CS) I/O polarity control register (PC) Raster color register (RC) Extra font color register (EC) Border color register (FC) Window H register 1 (WH1) Window L register 1 (WL1) Window H register 2 (WH2) Window L register 2 (WL2)
SYC5 SYC4 SYC3 SYC2 SYC1 SYC0
DSC37 DSC36 DSC35 DSC34 DSC33 DSC32 DSC31 DSC30
AD/INT3 INT3 SEL POL
0
INT2 INT1 RE3 POL POL
0
0
0
0
0
SM5 RE5 SM4 RE3 RE2 RE1 SM0 SM3 SM2 SM1
0
AD/INT3 PC7 SEL AD/INT3 RC7 SEL
CS6 RE5 CS4 RE3 RE2 RE1 CS0 CS3 CS2 CS1 POL CS5 PC6 RE5 PC4 RE3 RE2 RE1 PC0 PC5 0 PC2 PC1 POL RC6 RE5 POL RC5 RE5
INT3 INT3
INT3
1
0
0
0 0 0 0
0 0 0 0
RC2 RC1 RE2 RE1 RC0 RE2 RE1 EC0 EC2 EC1
0
0
0
FC2 FC1 FC0
WH17 WH16 WH15 WH14 WH13 WH12 WH11 WH10 WL17 WL16 WL15 WL14 WL13 WL12 WL21 WL20 WH21 WH20 WL21 WL20
? ? ? ? ? ? ? ? 0016 ? ?0 0016 0716 FF16 0016 0016 0016 ? 0016 0016 ? ? 0016 00 0016 0016 0016 0016 ? ? ? ?
0
0
0
0
0
0
117
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
s SFR2 area (addresses 22016 to 24816)
< Bit allocation > < State immediately after reset >
:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 22016 22116 22216 22316 22416 22516 22616 22716 22816 22916 22A16 22B16 22C16 22D16 22E16 22F16 23016 23116 23216 23316 23416 23516 23616 23716 23816 23916 23A16 23B16 23C16 23D16 23E16 23F16 24016 24116 24216 24316 24416 24516 24616 24716 24816 Register
b7
Bit allocation
b0 b7
State immediately after reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
b0
Vertical position register 11 (VP11) Vertical position register 12 (VP12) Vertical position register 13 (VP13) Vertical position register 14 (VP14) Vertical position register 15 (VP15) Vertical position register 16 (VP16) Vertical position register 17 (VP17) Vertical position register 18 (VP18) Vertical position register 19 (VP19) Vertical position register 110 (VP110) Vertical position register 111 (VP111) Vertical position register 112 (VP112) Vertical position register 113 (VP113) Vertical position register 114 (VP114) Vertical position register 115 (VP115) Vertical position register 116 (VP116) Vertical position register 21 (VP21) Vertical position register 22 (VP22) Vertical position register 23 (VP23) Vertical position register 24 (VP24) Vertical position register 25 (VP25) Vertical position register 26 (VP26) Vertical position register 27 (VP27) Vertical position register 28 (VP28) Vertical position register 29 (VP29) Vertical position register 210 (VP210) Vertical position register 211 (VP211) Vertical position register 212 (VP212) Vertical position register 213 (VP213) Vertical position register 214 (VP214) Vertical position register 215 (VP215) Vertical position register 216 (VP216) DA-H register (DA-H) DA-L register (DA-L) ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR)
VP117 VP116 VP1 15 VP114 VP1 13 VP112 VP1 11 VP1 10 VP127 VP126 VP1 25 VP124 VP1 23 VP122 VP1 21 VP1 20 VP137 VP136 VP1 35 VP134 VP1 33 VP132 VP1 31 VP1 30 VP147 VP146 VP1 45 VP144 VP1 43 VP142 VP1 41 VP1 40 VP157 VP156 VP1 55 VP154 VP1 53 VP152 VP1 51 VP1 50 VP167 VP166 VP1 65 VP164 VP1 63 VP162 VP1 61 VP1 60 VP177 VP176 VP1 75 VP174 VP1 73 VP172 VP1 71 VP1 70 VP187 VP186 VP1 85 VP184 VP1 83 VP182 VP1 81 VP1 80 VP197 VP196 VP1 95 VP194 VP1 93 VP192 VP1 91 VP1 90
VP1107 VP1106 VP1 105 VP1104 VP1103 VP1102 VP1101 VP1100 VP1117 VP1116 VP1 115 VP1114 VP1113 VP1112 VP1111 VP1110 VP1127 VP1126 VP1 125 VP1124 VP1123 VP1122 VP1121 VP1120 VP1137 VP1136 VP1 135 VP1134 VP1133 VP1132 VP1131 VP1130 VP1147 VP1146 VP1 145 VP1144 VP1143 VP1142 VP1141 VP1140 VP1157 VP1156 VP1 155 VP1154 VP1153 VP1152 VP1151 VP1150 VP1167 VP1166 VP1 165 VP1164 VP1163 VP1162 VP1161 VP1160 VP211 VP210 VP221 VP220 VP231 VP230 VP241 VP240 VP251 VP250 VP261 VP260 VP271 VP270 VP281 VP280 VP291 VP290 VP2101 VP2100 VP2111 VP2110 VP2121 VP2120 VP2131 VP2130 VP2141 VP2140 VP2151 VP2150 VP2161 VP2160
0
0
?
0 0016
0 0
RCR1 RCR0
0
0
?? 0016 0016 0016 0016 0016 0016 0016
?
?
?
118
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Internal State of Processor Status Register and Program Counter at Reset
< Bit allocation >
< State immediately after reset >
:
Name
Function bit
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation
b0 b7
State immediately after reset
b0
N
V
T
B
D
I
Z
C
?
????1?? Contents of address FFFF16 Contents of address FFFE16
119
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows: Note : The following registers are the EPROM version's registers. They are different from the MASK version's.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00
Bit attributes (Note 2) Bits Values immediately after reset release (Note 1)
CPU mode register (CPUM) (CM) [Address FB 16] Name Processor mode bits 0, 1 (CM0, CM1) B Functions
b1 b0
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 0 1 RW RW RW 0 RW
2
Stack page selection bit (Note) (CM2)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." Nothing is assigned.1 This bit is write disable bit. When this bit is read out, the value is "0." b7 b6 6, 7 Clock switch bits (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned Notes 1: Values immediately after reset release 0******"0" after reset release 1******"1" after reset release ?******Indeterminate after reset release 5
2: Bit attributes******The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : W******Write R******Read ******Write enabled ******Read enabled ! ******Read disabled ! ******Write disabled V ******"0" can be set by software, but "1" cannot be set.
120
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00C116, 00C316, 00C516]
B 0 1 2 3 4 5 6 7
Name Port Pi direction register
Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Port Pi Direction Register
Addresses 00C116, 00C316, 00C516
Port P3 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C716]
B 0 1 2 to 5 6 7
Name Port P3 direction register
Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode
After reset R W 0 0 0 RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Timer 3 count source selection bit (T3SC) Ports P63, P64 selection bit (P6IM) Refer to Timer mode register 2 (address 00F516). Refer to clock source control register (address 021616).
0 0
RW RW
Port P3 Direction Register
Address 00C716
121
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Port P4 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Port P4 direction register (D4) [Address 00C9 16]
B 0
Name Fix this bit to "0."
Functions
After reset R W
0
RW
1 to 4, Nothing is assigned. These bits are write disable bits. 7 When these bits are read out, the values are "0." 5 6 Port P45 selection bit Port P46 selection bit 0: SOUT pin 1: Input port P45 0: SCLK pin 1: Input port P46
0 0 0
R-- RW RW
Port P4 Direction Register
Address 00C916
OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 OSD port control register (PF) [Address 00CB16]
B
Name
Functions
After reset R W 0 RW RW RW RW RW RW
0, 1, Fix these bits to "0." 7 2 3 4 5 6 Port P52 output signal selection bit (R) Port P53 output signal selection bit (G) Port P54 output signal selection bit (B) Port P55 output signal selection bit (OUT1) Port P10 output signal selection bit (OUT2) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 0 : Port P10 output 1 : OUT2 signal output (Note)
0
0 0 0 0
Note. Set bit 0 of Port P1 direction register (address 00C3 16) to "1" (output mode).
OSD Port Control Register
Address 00CB16
122
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
OSD Control Register
b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (OC) [Address 00CE16] B Name Functions After reset R W 0 0 0 0 RW RW RW RW
0 : All-blocks display off 0 OSD control bit (OC0) (See note 1) 1 : All-blocks display on 1 Scan mode selection 0 : Normal scnan mode 1 : Bi-scan mode bit (OC1) 2 Border type selection 0 : All bordered bit (OC2) 1 : Shadow bordered (See note 2) 3 Flash mode selection 0 : Color signal of character background bit (OC3) part does not flash 1 : Color signal of character background part flashes 0 : OFF 1 : ON 0 : OFF 1 : ON
b7 b6
4 Automatic solid space control bit (OC4) 5 Window control bit (OC5) 6, 7 Layer mixing control bits (OC6, OC7) (See note 3)
0 0
RW RW
0 0: Logic sum (OR) of layer 1's color and layer 2's color 0 1: Layer 1's color has priority 1 0: Layer 2's color has priority 1 1: Do not set.
0
RW
Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next V SYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : Set "00" during displaying extra fonts.
OSD Control Register
Address 00CE16
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00CF16 ] B Name Functions Horizontal display start positions
4TOSC ! (setting value of high-order 4 bits ! 161 + setting value of low-order 4 bits ! 160 )
After reset R W 0 RW
0 Control bits of horizontal to display start positions 7 (HP0 to HP7)
Notes 1. The setting value synchronizes with the V SYNC. 2. TOSC = OSD oscillation period.
Horizontal Position Register
Address 00CF16
123
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Block Control register i
b7 b6 b5 b4 b3 b2 b1 b0 Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16](See note 1) B Name
b1 b0
Functions 0 0 1 1 0: Display OFF 1: OSD mode 0: CC mode 1: EXOSD mode
After reset
RW
0, 1 Display mode selection bits (BCi0, BCi1)
Indeterminate R W
2
Border control bit (BCi2)
0: Border OFF 1: Border ON
b6 b5 b4 0 0 1 1 0 0 1 1 0 0 1 1 -- -- 0 0 1 1 b3 CS6 Pre-divide ratio 0 0 1-- !1 1 0 1 !2 0-- 1 0 1 !3 0-- 1 !1 0 10 0 !2 11 0 1 Dot size Display layer
Indeterminate R W Indeterminate R W
3, 4 Dot size selection bits (BCi3, BCi4)
0
0
0
1
5, 6 Pre-divide ratio * layer selection bit (BCi5, BCi6)
1
0
1
1
1
1
1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H 1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H Layer1 3Tc ! 3H 1Tc ! 1/2H 1Tc ! 1H 2Tc ! 2H 3Tc ! 3H 1Tc ! 1/2H 1Tc ! 1H 1Tc ! 1/2H Layer2 1Tc ! 1H 1.5Tc ! 1/2H 1.5Tc ! 1H
Indeterminate R W
7
OUT2 output control bit (BCi7) (See note 2)
BC17: Window top boundary BC27: Window bottom boundary
Indeterminate R W
Notes 1: Note that MASK version the block control registers at addresses 00D016 to 00DB16 when programming. 2: Bit 4 of the color code 1 controls OUT1 output when bit 7 is "0". Bit 4 of the color code 1 controls OUT2 output when bit 7 is "1". 3: CS6 : Bit 6 of the clock control register (address 0216 16) 4: Tc : Pre-devided clock period for OSD 5: H : Hsync
Block Control Register i
Addresses 00D016 to 00DB16
124
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Caption Position Register
b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 Caption Position Register (CP) [Address 00E0 16]
B
Name
Functions
After reset 0
RW RW
0 Specification main data to slice line (CP0 to CP4) 4 5, 6 Fix these bits to "0."
0
RW
7
Fix this bit to "0."
0
RW
Caption Position Register
Address 00E016
Start Bit Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Start bit position register (SP) [Address 00E116]
B 0 to 6
Name
Functions
After reset 0
RW RW
Start bit generating time Time from a falling of the horizontal (SP0 to SP6) synchronous signal to occurrence of a start bit = 4 ! set value ("0016" to "7F16") ! reference clock period DSC1 bit 7 control bit (SP7) 0 : Generation of 16 pulses 1 : Generation of 16 pulses and detection of clock run-in pulse (4 to 6 pulses)
7
0
RW
Start Bit Position Register
Address 00E116
Window Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 Window register (WN) [Address 00E2 16]
B 0 to 5
Name Window start time (WN0 to WN5)
Functions Time from a falling of the horizontal synchronous signal to start of the window = 4 ! set value ("0016" to "3F16") ! reference clock period
After reset 0
RW RW
6, 7 Fix these bits to "0."
0
RW
Window Register
Address 00E216
125
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Sync Slice Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 1 0 1 Sync slice register (SSL) [Address 00E3 16]
B 0, 2
Name Fix these bits to "1."
Functions
After reset 0
RW RW
1, Fix these bits to "0." 3 to 6 7 Vertical synchronous signal (Vsep) generating method selection bit (SSL7) 0: Method 1 1: Method 2
0
RW
0
RW
Sync Slice Register
Address 00E316
Clock Run-in Register 1
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 Clock run-in register 1 (CR1) [Address 00E6 16]
B 0 to 3 4, 6
Name Clock run-in count value of main-data slice line (CR10 to CR13) Fix these bits to "1."
Functions
After reset 0
RW RW
0
RW
5, 7
Fix these bits to "0."
0
RW
Clock Run-in Register 1
Address 00E616
Clock Run-in Register 2
b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 1 Clock run-in register 2 (CR2) [Address 00E716]
B
Name
Functions
After reset 0
RW RW
0, Fix these bits to "1." 2 to 4, 7 1 Start bit detecting method selection bit (CR21) Fix these bits to "0." 0: Method 1 1: Method 2
0
RW
5, 6
0
RW
Clock Run-in Register 2
Address 00E716
126
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Clock Run-in Detect Register i
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register i (CRDi) (i=1, 3) [Addresses 00E816, 020816]
B 0 to 2 3 to 7
Name Test bits Read-only
Functions
After reset
0
RW RW
Clock run-in detection bits (CRDi3 to CRDi7)
Number of reference clock s to be counted one clock runin pulse period
0
R--
Clock Run-in detect Register i
Addresses 00E816, 020816
Clock Run-in Detect Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in detect register 2 (CRD2) [Address 00E916]
B 0 to 2
Name Clock run-in pulses for sampling (CRD20 to CRD22) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions b0 0 : Not available 1 : 1st pulse 0 : 2nd pulse 1 : 3rd pulse 0 : 4th pulse 1 : 5th pulse 0 : 6th pulse 1 : 7th pulse
After reset 0
RW RW
3 to 7
Data clock generating time (CRD23 to CRD27)
Time from detection of a start bit to occurrence of a data clock = (13 + set value) ! reference clock period
0
RW
Clock Run-in detect Register 2
Address 00E916
127
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data Slicer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Data slicer control register 1(DSC1) [Address 00EA16]
B 0
Bit Data slicer control bit (DSC10)
Functions 0: Data slicer stopped 1: Data slicer operating b2 0 0 1 1 Field of main b1 data slice line 0 F2 1 F1 0 F1 and F2 1 F1 and F2 Field for setting refernce voltage F2 F1 F2 F1
After reset 0 0
RW RW RW
1, 2 Field to be sliced data selection bit (DSC11, DSC12)
3, 4, Fix these bits to "0." 6 5 Field determination flag (DSC15) 0 : Hsep Vsep
0
RW
Indeterminate R --
1 : Hsep Vsep 7 Data latch completion flag for caption data in main data slice line (DSC17) 0: Data is not yet latched 1: Data is latched
Indeterminate R W
Definition of fields 1 (F1) and 2 (F2) F1 : Hsep VSYNC Vsep
F2 : Hsep VSYNC Vsep
Data Slicer Control Register 1
Address 00EA16
128
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Data slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Data slicer Control register 2 (DSC2) [Address 00EB16]
B 0
Name Timing signal generating circuit control bit (DSC20) Reference clock source selection bit (DSC21)
Functions 0: Stopped 1: Operating 0: Video signal 1: HSYNC signal Read-only
After reset 0
RW RW
1
0
RW
2, 7 Test bit 3, 4, Fix these bits to "0." 6 5
Indeterminate R -- 0 RW
V-pulse shape determination 0: Match flag (DSC25) 1: Mis match
Indeterminate R --
Data Slicer Control Register 2
Address 00EB16
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
A-D control register (ADCON) [Address 00EF16]
B
0 to 2
Name
Analog input pin selection bits (ADIN0 to ADIN2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0: Do not set. 1:
After reset R W
0
RW
3 4 6
A-D conversion completion bit (ADSTR) VCC connection selection bit (ADVREF)
0: Conversion in progress 1: Convertion completed 0: OFF 1: ON
Indeterminate Indeterminate Indeterminate
RW RW R-- R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.
5, 7 Fix these bits to "0."
0
A-D Control Register
Address 00EF16
129
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B Name 0 Timer 1 count source selection bit 1 (TM10) 1 Timer 2 count source selection bit 1 (TM11) Timer 1 count stop bit (TM12) Timer 2 count stop bit (TM13) Timer 2 count source selection bit 2 (TM14) Timer 1 count source selection bit 2 (TM15) Timer 5 count source selection bit 2 (TM16) Timer 6 internal count source selection bit (TM17) Functions After reset R W 0: f(XIN)/16 or f(XCIN)/16 (Note) 0 RW 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow 0: f(XIN)/4096 or f(XCIN)/4096 (See note) 1: External clock from TIM2 pin 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow 0 RW
2 3 4
0 0 0
RW RW RW
5
0
RW
6 7
0 0
RW RW
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer Mode Register 1
Address 00F416
130
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Timer Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) Functions (b6 at address 00C716) b0 0 0 : f(XIN)/16 or f(XCIN)/16 (See note) 0 1 : f(XCIN) 1 0: External clock from TIM3 pin 1 1: b4 0 0 1 1 b1 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) 0 : f(XIN)/2 or f(XCIN)/2 (See note) 1 : f(XCIN) After reset R W 0 RW
1, 4 Timer 4 count source selection bits (TM21, TM24)
0
RW
2 3 5 6 7
Timer 3 count stop bit (TM22) Timer 4 count stop bit (TM23) Timer 5 count stop bit (TM25) Timer 6 count stop bit (TM26) Timer 5 count source selection bit 1 (TM27)
0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Count source selected by bit 6 of TM1
0 0 0 0 0
RW RW RW RW RW
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer Mode Register 2
Address 00F516
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00F616]
2
B 0 to 7
Name D0 to D7
Functions This is an 8-bit shift register to store receive data and write transmit data.
After reset
RW
Indeterminate R W
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
Address 00F616
131
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00F716] B
0 1 to 7
Name
Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write
Functions
After reset R W
0 0
R-- RW
The address data transmitted from the master is compared with the contents of these bits.
I2C Address Register
Address 00F716
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " 0 : No general call detected 1 : General call detected 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
After reset R W
Indeterminate 0 0 0 0 0 0
R-- R-- R-- R-- R-- RW RW
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
I2C Status Register
Address 00F816
132
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D : address 00F9 16)
B
0 to 2
Name
Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0: 1: 0: 1: 0: 1: 0: 1:
Functions
8 7 6 5 4 3 2 1
After reset R W
0
RW
3 4 5
I2 C-BUS interface use enable bit (ESO) Data format selection bit (ALS) Addressing format selection bit (10BIT SAD)
0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits between I2C-BUS interface and ports
Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output.
I2C Control Register
Address 00F916
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2 : address 00FA 16)
B
0 to 4
Name
Functions
High speed clock mode
After reset R W
0
SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) CCR4-CCR0 mode 00 to 02 03 04 05 06 1D 1E 1F ...
RW
Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3
500/CCR value
333 250 400 (See note) 166
1000/CCR value
17.2 16.6 16.1
34.5 33.3 32.3 0
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock
RW RW RW
6 7
0 0
Note: At 4000kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
I2C Clock Control Register
Address 00FA16
133
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11 00 CPU mode register (CPUM) (CM) [Address FB16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions
b1 b0
After reset R W 0 RW
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW RW
2
Stack page selection bit (CM2) (See note)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." 5 XCOUT drivability selection bit (CM5) 6 Main Clock (X IN-XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: XIN-XOUT selected (high-speed mode) 1: XCIN-XCOUT selected (high-speed mode)
1 0
0
RW
Note: This bit is set to "1" after the reset release.
CPU Mode Register
Address 00FB16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV R--
0 : No interrupt request issued Timer 1 interrupt 1 : Interrupt request issued request bit (TM1R) Timer 2 interrupt 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 : No interrupt request issued Timer 3 interrupt 1 : Interrupt request issued request bit (TM3R) 0 : No interrupt request issued Timer 4 interrupt 1 : Interrupt request issued request bit (TM4R) OSD interrupt request 0 : No interrupt request issued 1 : Interrupt request issued bit (CRTR) 0 : No interrupt request issued VSYNC interrupt request bit (VSCR) 1 : Interrupt request issued A-D conversion * INT3 0 : No interrupt request issued interrupt request bit (ADR) 1 : Interrupt request issued Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
V: "0" can be set by software, but "1" cannot be set.
Interrupt Request Register 1
Address 00FC16
134
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B 0 Name Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 0 RV RV RV RV RV RV RV RW
INT1 interrupt request bit (INT1R) 1 Data slicer interrupt request bit (DSR) 2 Serial I/O interrupt request bit (SIOR) 3 f(XIN)/4096 interrupt request bit (1MSR) 4 INT2 interrupt request bit (INT2R) 5 Multi-master I 2C-BUS interrupt request bit (IICR) 6 7 Timer 5 * 6 interrupt request bit (T56R) Fix this bit to "0."
V: "0" can be set by software, but "1" cannot be set.
Interrupt Request Register 2
Address 00FD16
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 1 2 3 4 5 6 7 Name Timer 1 interrupt enable bit (TM1E) Timer 2 interrupt enable bit (TM2E) Timer 3 interrupt enable bit (TM3E) Timer 4 interrupt enable bit (TM4E) OSD interrupt enable bit (CRTE) VSYNC interrupt enable bit (VSCR) A-D conversion * INT3 interrupt enable bit (ADE) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Interrupt Control Register 1
Address 00FE16
135
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 1 2 3 4 5 6 7 Name INT1 interrupt enable bit (INT1E) Data slicer interrupt enable bit (DSR) Serial I/O interrupt enable bit (SIOE) f(XIN)/4096 interrupt enable bit (1MSE) INT2 interrupt enable bit (INT2E) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Multi-master I 2C-BUS interface 0 : Interrupt disabled interrupt enable bit (IICE) 1 : Interrupt enabled Timer 5 * 6 interrupt enable bit (T56E) Timer 5 * 6 interrupt switch bit (TM56S) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6
Interrupt Control Register 2
Address 00FF16
Clock Run-in Register 3
b7 b6 b5 b4 b3 b2 b1 b0 Clock run-in register 3 (CR3) [Address 020916]
B 0 to 3 4
Name Clock run-in count value of sub-data slice line (CR30 to CR33) Data latch completion flag for caption data in subdata slice line (CR34)
Functions
After reset 0
RW RW
0: Data is not latched yet 1: Data is latched
Indeterminate R W
5
Data slice line selection bit for interrupt request (CR35) Interrupt mode selection bit (CR36)
0: Main data slice line 1: Sub- data slice line 0: Interrupt occurs at end of data slice line 1: Interrupt occurs at completion of caption data latch
Indeterminate R W
6
Indeterminate R W
7
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Indeterminate R --
Clock Run-in Register 3
Address 020916
136
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
PWM Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM mode register 1 (PN) [Address 020A16] B 0 1 2 3 4 to 7 Name PWM counts source selection bit (PN0) DA/P03 output selection bit (PN1) DA output polarity selection bit (PN2) PWM output polarity selection bit (PN3) Functions 0 : Count source supply 1 : Count source stop 0 : P03 output 1 : DA output 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity After reset 0 0 0 0 RW RW RW RW RW
Nothing is assigned. These bits are write disable bits. Indeterminate R -- When these bits are read out, the values are "0."
PWM Mode Register 1
Address 020A16
PWM Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 PWM mode register 2 (PW) [Address 020B16] B Name 0 P04/PWM0 output selection bit (PW0) 1 2 3 4 5 6 7 P05/PWM1 output selection bit (PW1) P06/PWM2 output selection bit (PW2) P07/PWM3 output selection bit (PW3) P00/PWM4 output selection bit (PW4) P01/PWM5 output selection bit (PW5) P02/PWM6 output selection bit (PW6) Fix this bit to "0." Functions 0 : P04 output 1 : PWM0 output 0 : P05 output 1 : PWM1 output 0 : P06 output 1 : PWM2 output 0 : P07 output 1 : PWM3 output 0 : P00 output 1 : PWM4 output 0: P01 output 1: PWM5 output 0: P02 output 1: PWM6 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
PWM Mode Register 2
Address 020B16
137
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Sync Pulse Counter Register
b7 b6 b5 b4 b3 b2 b1 b0 Sync pulse counter register (SYC) [Address 020F16]
B 0 to 4 5
Name Count value (SYC0 to SYC4) Count source (SYC5)
Functions
After reset 0
RW R--
0: HSYNC signal 1: Composite sync signal
0
RW
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Sync Pulse Counter Register
Address 020F16
Data Slicer Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0 Data slicer control register 3 (DSC3) [Address 021016]
B 0
Bit Line selection bit for slice voltage (DSC30)
Functions 0: Main data slice line 1: Sub-data slice line b2 0 0 1 1 Field of subb1 data slice line 0 F2 1 F1 0 F1 and F2 1 F1 and F2 Field for setting refernce voltage F2 F1 F2 F1
After reset
0
RW
RW
1, 2 Field to be sliced data selection bit (DSC31, DSC32)
0
RW
3 to 7
Setting bit of sub-data slice line (DSC33 to DSC37)
0
RW
Definition of fields 1 (F1) and 2 (F2) F1 : Hsep VSYNC Vsep
F2 : Hsep VSYNC Vsep
Data Slicer Control Register 3
Address 021016
138
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 Interrupt input polarity register (IP) [Address 0212 16]
B
Name
Functions
After reset 0
RW RW RW RW RW
0 to 2, Fix these bits to "0." 5 3 4 6 INT1 polarity switch bit (INT1POL) INT2 polarity switch bit (INT2POL) INT3 polarity switch bit (INT3POL) A-D conversion * INT3 interrupt source selection bit (RE7) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
0 0 0
7
0
RW
Interrupt Input Polarity Register
Address 021216
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Serial I/O mode register (SM) [Address 021316] B Name b1 0 0 1 1 Functions b0 0: f(XIN)/4 or f(XCIN)/4 1: f(XIN)/16 or f(XCIN)/16 0: f(XIN)/32 or f(XCIN)/32 1: f(XIN)/64 or f(XCIN)/64 After reset R W RW 0
0, 1 Internal synchronous clock selection bits (SM0, SM1)
2 3
Synchronous clock selection bit (SM2) Port function selection bit (SM3) Port function selection bit (SM4) Transfer direction selection bit (SM5)
0: External clock 1: Internal clock 0: P11, P13 1: SCL1, SDA1 0: P12, P14 1: SCL2, SDA2 0: LSB first 1: MSB first
0
RW
0
RW
4 5
0 0 0
RW RW RW
6, 7 Fix these bits to "0."
Serial I/O Mode Register
Address 021316
139
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Clock Source Control Register
b7 b6 b5 b4 b3 b2 b1 b0 Clock source control register (CS) [Address 021616]
B 0
Name CC mode clock selection bit (CS0)
Functions 0: Data slicer clock 1: OSC1 clock
b2 b1
After reset R W 0 0 RW RW
1, 2 OSD mode clock selection bits (CS1, CS2)
0 0 1 1
0: Data slicer clock 1: OSC1 clock 0: Main clock (See note 1) 1: Do not set 0 0 RW RW
3
EXOSD mode clock selection bit (CS3)
0: Data slicer clock 1: OSC1 clock
b5 b4
4, 5 OSD oscillating mode selection bits (CS4, CS5)
0 0: 32 kHz oscillating mode 0 1: Input ports P63, P64 (See note 2) 1 0: LC oscillating mode 1 1: Ceramic * quartz-crystal oscillating mode 0: ! 1 1: ! 2 0 0
6 7
Pre-divide ratio of layer 2 selection bit (CS6) Test bit (See note 3)
RW RW
Notes 1: When setting "102," main clock is set as a clock in the CC mode and EXOSD mode regardless of bits 0, 3. 2: When selecting input ports P63 and P64, set bit 7 at address 00C716 to "0." 3: Be sure to set bit 7 to "0" for program of the mask and the EPROM versions. For the emulator MCU version (M37274ERSS), be sure to set bit 7 to "1" when using the data slicer clock for software debugging.
Clock Source Control Register
Address 021616
140
MITSUBISHI MICROCOMPUTERS
nge ion. icat to cha ecif l sp ubject a a fin re s not mits a li is is : Th mentic ice Not e para Som
PRE
L
A IMIN
RY
.
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
I/O Polarity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
I/O polarity control register (PC) [Address 021716]
B 0 1 2 3 4 5 6
Name HSYNC input polarity switch bit (PC0) VSYNC input polarity switch bit (PC1) R, G, B output polarity switch bit (PC2) Fix this bit to "0". OUT1 output polarity switch bit (PC4) OUT2 output polarity switch bit (PC5) Display dot line selection bit (PC6) (See note)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity output 1 : Negative polarity output
After reset R W 0 0 0 0 RW RW RW R-- RW RW RW
0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0:" " 1:" " " at even field " at odd field " at even field " at odd field
0 0 0
7
Field determination flag (PC7)
0 : Even field 1 : Odd field
1
R--
Note: Refer to Figure 79.
I/O Polarity Control Register
Address 021716
Raster Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Raster color register (RC) [Address 021816] B 0 1 2 Name Raster color R control bit (RC0) Raster color G control bit (RC1) Raster color B control bit (RC2) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset R W 0 0 0 0 0 : No output 1 : Output 0 : No output 1 : Output 0 : Interrupt occurs at end of OSD or EXOSD block display 1 : Interrupt occurs at end of CC mode block display 0 0 0 RW RW RW R-- RW RW RW
3, 4 Fix these bits to "0." 5 Raster color OUT1 control bit (RC5)
6 Raster color OUT2 control bit (RC6) 7 OSD interrupt source selection bit (RC7)
Raster Color Register
Address 021816
141
MITSUBISHI MICROCOMPUTERS
n. ange. atio h cific ct to c spe je inal re sub taf sa o is n limit This entic m ice: Not e para Som
PR
IN LIM E
ARY
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Extra Font Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Extra font color register (EC) [Address 021916] B 0 1 2 Name Extra font color R control bit (EC0) Extra font color G control bit (EC1) Extra font color B control bit (EC2) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset 0 0 0 0 0 RW RW RW RW RW R--
3, 4 Fix these bits to "0." Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
5 to 7
Extra Font Color Register
Address 021916
Border Color Register
b7 b6 b5 b4 b3 b2 b1 b0 00 Border color register (FC) [Address 021B16] B 0 1 2 Name Border color R control bit (FC0) Border color G control bit (FC1) Border color B control bit (FC2) Functions 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output After reset 0 0 0 0 0 RW RW RW RW RW R--
3, 4 Fix these bits to "0." Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
5 to 7
Border Color Register
Address 021B16
142
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Window H Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Window H register 1 (WH1) [Address 021C16] B Name Functions After reset RW
0 Control bits of window to top boundary 7 (WN10 to WN17) (See note 1)
Top boundary position (low-order 8 bits) Indeterminate R W TH ! (setting value of low-order 2 bits of WH2 ! 162 + setting value of high-order 4 bits of WH1 ! 161 + setting value of low-order 4 bits of WH1 ! 160)
Notes 1: Set values except "00 16" to the WH1 when WH2 is "00 16." 2: TH is cycle of HSYNC. 3: WH2: Window H register 2
Window H Register 1
Address 021C16
Window L Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Window L register 1 (WL1) [Address 021D16] B Name Functions After reset RW
0 Control bits of window to top boundary 7 (WL10 to WL17) (See note 1)
Indeterminate R W Top boundary position (low-order 8 bits) TH ! (setting value of low-order 2 bits of WL2 ! 162 + setting value of high-order 4 bits of WL1 ! 161 + setting value of low-order 4 bits of WL1 ! 160)
Notes 1: Set values fit for the following condition: (WH1+WH2 !162)<(WL1+WL2! 162) 2: TH is cycle of HSYNC. 3: WL2: Window L register 2
Window L Register 1
Address 021D16
Window H Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Window H register 2 (WH2) [Address 021E16] B Name Functions After reset RW
0, 1 Control bits of window top boundary (WN20 ,WN21) (See note 1)
Top boundary position (high-order 2 bits) Indeterminate R W TH ! (setting value of low-order 2 bits of WH2 ! 162 + setting value of high-order 4 bits of WH1 ! 161 + setting value of low-order 4 bits of WH1 ! 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Set values except "00 16" to the WH1 when WH2 is "00 16." 2: TH is cycle of HSYNC. 3: WH1: Window H register 1
Window H Register 2
Address 021E16
143
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
Window L Register 2
b7 b6 b5 b4 b3 b2 b1 b0 Window L register 2 (WL2) [Address 021F16] B Name Functions After reset RW
0, 1 Control bits of window top boundary (WL20, WL21) (See note 1)
Top boundary position (high-order 2 bits) Indeterminate R W TH ! (setting value of low-order 2 bits of WL2 ! 162 + setting value of high-order 4 bits of WL1 ! 161 + setting value of low-order 4 bits of WL1 ! 160)
2 Nothing is assigned. These bits are write disable bits. Indeterminate R -- to When these bits are read out, the values are indeterminate. 7 Notes 1: Set values fit for the following condition: (WH1+WH2 !162)<(WL1+WL2! 162) 2: TH is cycle of HSYNC. 3: WL1: Window L register 1
Window L Register 2
Address 021F16
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16] B Name Functions After reset R W 0 Control bits of vertical Vertical display start positions Indeterminate R W to display start positions (low-order 8 bits) 7 (VP1i0 to VP1i7) TH ! (See note 1) (setting value of low-order 2 bits of VP2i ! 162 + setting value of low-order 4 bits of VP1i ! 161 + setting value of low-order 4 bits of VP1i ! 160) Notes 1: Set values except "00 16" "0116" to VP1i when VP2i is "00 16." 2: TH is cycle of HSYNC.
Vertical Position Register 1i
Addresses 022016 to 022B16
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16] B Name Functions After reset RW
0, 1 Control bits of vertical Vertical display start positions Indeterminate R W display start positions (high-order 2 bits) TH ! (VP1i0, VP1i1) (See note 1) (setting value of low-order 2 bits of VP2i ! 162 + setting value of low-order 4 bits of VP1i ! 161 + setting value of low-order 4 bits of VP1i ! 160) 2 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are indeterminate. 7 Indeterminate R --
Notes 1: Set values except "00 16" "0116" to VP1i when VP2i is "00 16." 2: TH is cycle of HSYNC.
Vertical Position Register 2i
Addresses 023016 to 023B16
144
MITSUBISHI MICROCOMPUTERS
e. n. atio chang cific to spe bject l fina re su a ot a is n limits This entic : tice aram No e p Som
PRE
L
R INA IM
Y
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0 0 0
ROM correction enable register (RCR) [Address 024616] B
0 1
Name
Block 1 enable bit (RC0) Block 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0
RW RW RW R--
2, 3 Fix these bits to "0."
0
4 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
ROM Correction Enable Register
Address 024616
145
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
*
* *
*
(c) 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Nov. 1997. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
M37274EFSP DATA SHEET
Revision Description Rev. date 971130
(1/1)